cell_port | cell_port_list_rules ',' cell_port;
cell_port:
- /* empty */ {
+ attr {
AstNode *node = new AstNode(AST_ARGUMENT);
astbuf2->children.push_back(node);
+ free_attr($1);
} |
- expr {
+ attr expr {
AstNode *node = new AstNode(AST_ARGUMENT);
astbuf2->children.push_back(node);
- node->children.push_back($1);
+ node->children.push_back($2);
+ free_attr($1);
} |
- named_port '(' ')' | // not connected
- named_port '(' expr ')' {
- ($1)->children.push_back($3);
+ attr '.' TOK_ID '(' expr ')' {
+ AstNode *node = new AstNode(AST_ARGUMENT);
+ node->str = *$3;
+ astbuf2->children.push_back(node);
+ node->children.push_back($5);
+ delete $3;
+ free_attr($1);
} |
- named_port {
- // SV implied port
- if (!sv_mode)
- frontend_verilog_yyerror("Implicit .name port connection in port list (%s). This is not supported unless read_verilog is called with -sv!", $1->str.c_str());
- auto id_node = new AstNode(AST_IDENTIFIER);
- id_node->str = ($1)->str;
- ($1)->children.push_back(id_node);
- };
-
-named_port:
- '.' TOK_ID {
+ attr '.' TOK_ID '(' ')' {
AstNode *node = new AstNode(AST_ARGUMENT);
- node->str = *$2;
- delete $2;
+ node->str = *$3;
+ astbuf2->children.push_back(node);
+ delete $3;
+ free_attr($1);
++ } |
++ attr '.' TOK_ID {
++ AstNode *node = new AstNode(AST_ARGUMENT);
++ node->str = *$3;
+ astbuf2->children.push_back(node);
- $$ = node;
++ node->children.push_back(new AstNode(AST_IDENTIFIER));
++ node->children.back()->str = *$3;
++ delete $3;
++ free_attr($1);
};
always_stmt: