r600g: add eg db count control register.
authorDave Airlie <airlied@redhat.com>
Sat, 25 Sep 2010 10:23:44 +0000 (20:23 +1000)
committerDave Airlie <airlied@redhat.com>
Sat, 25 Sep 2010 12:14:08 +0000 (22:14 +1000)
src/gallium/drivers/r600/eg_hw_states.c
src/gallium/drivers/r600/eg_states_inc.h
src/gallium/winsys/r600/drm/eg_states.h

index 272972d41895552954841f3ef7b698a3750ba919..889eedadef55b82dd76a6f8487654f373340280f 100644 (file)
@@ -364,6 +364,7 @@ static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
        struct r600_screen *rscreen = rctx->screen;
        unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
        unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
+       unsigned db_count_control = 0;
        struct r600_shader *rshader;
        struct r600_query *rquery = NULL;
        boolean query_running;
@@ -439,7 +440,7 @@ static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
 
        if (query_running) {
                db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
-//             db_render_control |= S_028000_PERFECT_ZPASS_COUNTS(1);
+               db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
        }
 
        rstate->states[EG_DSA__DB_STENCIL_CLEAR] = 0x00000000;
@@ -455,7 +456,7 @@ static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
        rstate->states[EG_DSA__DB_SHADER_CONTROL] = db_shader_control;
        rstate->states[EG_DSA__DB_RENDER_CONTROL] = db_render_control;
        rstate->states[EG_DSA__DB_RENDER_OVERRIDE] = db_render_override;
-         
+       rstate->states[EG_DSA__DB_COUNT_CONTROL] = db_count_control;
        rstate->states[EG_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
        rstate->states[EG_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
        rstate->states[EG_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
index 9f8007c8e91e20446d9bc13e3749e73175a208b9..1379c11291f64e87d0f05a652dc3e70a73d4ec6e 100644 (file)
 #define EG_DSA__DB_DEPTH_CONTROL               7
 #define EG_DSA__DB_SHADER_CONTROL              8
 #define EG_DSA__DB_RENDER_CONTROL              9
-#define EG_DSA__DB_RENDER_OVERRIDE             10
-#define EG_DSA__DB_RENDER_OVERRIDE2            11
-#define EG_DSA__DB_SRESULTS_COMPARE_STATE0             12
-#define EG_DSA__DB_SRESULTS_COMPARE_STATE1             13
-#define EG_DSA__DB_PRELOAD_CONTROL             14
-#define EG_DSA__DB_ALPHA_TO_MASK               15
-#define EG_DSA_SIZE            16
+#define EG_DSA__DB_COUNT_CONTROL               10
+#define EG_DSA__DB_RENDER_OVERRIDE             11
+#define EG_DSA__DB_RENDER_OVERRIDE2            12
+#define EG_DSA__DB_SRESULTS_COMPARE_STATE0             13
+#define EG_DSA__DB_SRESULTS_COMPARE_STATE1             14
+#define EG_DSA__DB_PRELOAD_CONTROL             15
+#define EG_DSA__DB_ALPHA_TO_MASK               16
+#define EG_DSA_SIZE            17
 #define EG_DSA_PM4 128         
 
 /* EG_VS_SHADER */
index d87109fb801105738ddf8b54133e819ffd7717fb..ced7f147c0fd44feb14703e3c549ab5b5ba1f4b8 100644 (file)
@@ -164,6 +164,7 @@ static const struct radeon_register EG_names_DSA[] = {
        {0x00028800, 0, 0, "DB_DEPTH_CONTROL"},
        {0x0002880C, 0, 0, "DB_SHADER_CONTROL"},
        {0x00028000, 0, 0, "DB_RENDER_CONTROL"},
+       {0x00028004, 0, 0, "DB_COUNT_CONTROL"},
        {0x0002800C, 0, 0, "DB_RENDER_OVERRIDE"},
        {0x00028010, 0, 0, "DB_RENDER_OVERRIDE2"},
        {0x00028AC0, 0, 0, "DB_SRESULTS_COMPARE_STATE0"},