projects / gcc.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 7e89048)
rs6000: Rename 74 -> CR6_REGNO
authorSegher Boessenkool <segher@kernel.crashing.org>
Thu, 1 Sep 2016 22:26:05 +0000 (00:26 +0200)
committerSegher Boessenkool <segher@gcc.gnu.org>
Thu, 1 Sep 2016 22:26:05 +0000 (00:26 +0200)
* config/rs6000/altivec.md: Use CR6_REGNO instead of 74 throughout.
* config/rs6000/vector.md: Ditto.
* config/rs6000/vsx.md: Ditto.

From-SVN: r239946

gcc/ChangeLog patch | blob | history
gcc/config/rs6000/altivec.md patch | blob | history
gcc/config/rs6000/vector.md patch | blob | history
gcc/config/rs6000/vsx.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 223cf33121f92c108bc65c51e0fb17f8ac6955bc..ad0e95a58187952a4117b09bd7f5017761941c4d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2016-09-01  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/altivec.md: Use CR6_REGNO instead of 74 throughout.
+       * config/rs6000/vector.md: Ditto.
+       * config/rs6000/vsx.md: Ditto.
+
 2016-09-01  Eric Botcazou  <ebotcazou@adacore.com>
 
        * ipa-inline-analysis.c (param_change_prob): Get to the base object
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 25472c29725905c2e5a6cc9a0d2eab4bbd2f206c..480e64ec5ba0a0c00982534eb1499f474697648f 100644 (file)
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2274,7 +2274,7 @@
 ;; Compare vectors producing a vector result and a predicate, setting CR6 to
 ;; indicate a combined status
 (define_insn "*altivec_vcmpequ<VI_char>_p"
-  [(set (reg:CC 74)
+  [(set (reg:CC CR6_REGNO)
        (unspec:CC [(eq:CC (match_operand:VI2 1 "register_operand" "v")
                           (match_operand:VI2 2 "register_operand" "v"))]
                   UNSPEC_PREDICATE))
@@ -2286,7 +2286,7 @@
   [(set_attr "type" "veccmpfx")])
 
 (define_insn "*altivec_vcmpgts<VI_char>_p"
-  [(set (reg:CC 74)
+  [(set (reg:CC CR6_REGNO)
        (unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v")
                           (match_operand:VI2 2 "register_operand" "v"))]
                   UNSPEC_PREDICATE))
@@ -2298,7 +2298,7 @@
   [(set_attr "type" "veccmpfx")])
 
 (define_insn "*altivec_vcmpgtu<VI_char>_p"
-  [(set (reg:CC 74)
+  [(set (reg:CC CR6_REGNO)
        (unspec:CC [(gtu:CC (match_operand:VI2 1 "register_operand" "v")
                            (match_operand:VI2 2 "register_operand" "v"))]
                   UNSPEC_PREDICATE))
@@ -2310,7 +2310,7 @@
   [(set_attr "type" "veccmpfx")])
 
 (define_insn "*altivec_vcmpeqfp_p"
-  [(set (reg:CC 74)
+  [(set (reg:CC CR6_REGNO)
        (unspec:CC [(eq:CC (match_operand:V4SF 1 "register_operand" "v")
                           (match_operand:V4SF 2 "register_operand" "v"))]
                   UNSPEC_PREDICATE))
@@ -2322,7 +2322,7 @@
   [(set_attr "type" "veccmp")])
 
 (define_insn "*altivec_vcmpgtfp_p"
-  [(set (reg:CC 74)
+  [(set (reg:CC CR6_REGNO)
        (unspec:CC [(gt:CC (match_operand:V4SF 1 "register_operand" "v")
                           (match_operand:V4SF 2 "register_operand" "v"))]
                   UNSPEC_PREDICATE))
@@ -2334,7 +2334,7 @@
   [(set_attr "type" "veccmp")])
 
 (define_insn "*altivec_vcmpgefp_p"
-  [(set (reg:CC 74)
+  [(set (reg:CC CR6_REGNO)
        (unspec:CC [(ge:CC (match_operand:V4SF 1 "register_operand" "v")
                           (match_operand:V4SF 2 "register_operand" "v"))]
                   UNSPEC_PREDICATE))
@@ -2346,7 +2346,7 @@
   [(set_attr "type" "veccmp")])
 
 (define_insn "altivec_vcmpbfp_p"
-  [(set (reg:CC 74)
+  [(set (reg:CC CR6_REGNO)
        (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
                    (match_operand:V4SF 2 "register_operand" "v")]
                   UNSPEC_VCMPBFP))
@@ -3634,7 +3634,7 @@
                      (match_operand:V1TI 2 "register_operand" "")
                      (match_operand:QI 3 "const_0_to_1_operand" "")]
                     UNSPEC_BCD_ADD_SUB))
-   (clobber (reg:CCFP 74))]
+   (clobber (reg:CCFP CR6_REGNO))]
   "TARGET_P8_VECTOR"
   "bcd<bcd_add_sub>. %0,%1,%2,%3"
   [(set_attr "length" "4")
@@ -3646,7 +3646,7 @@
 ;; probably should be one that can go in the VMX (Altivec) registers, so we
 ;; can't use DDmode or DFmode.
 (define_insn "*bcd<bcd_add_sub>_test"
-  [(set (reg:CCFP 74)
+  [(set (reg:CCFP CR6_REGNO)
        (compare:CCFP
         (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "v")
                       (match_operand:V1TI 2 "register_operand" "v")
@@ -3665,7 +3665,7 @@
                      (match_operand:V1TI 2 "register_operand" "v")
                      (match_operand:QI 3 "const_0_to_1_operand" "i")]
                     UNSPEC_BCD_ADD_SUB))
-   (set (reg:CCFP 74)
+   (set (reg:CCFP CR6_REGNO)
        (compare:CCFP
         (unspec:V2DF [(match_dup 1)
                       (match_dup 2)
@@ -3699,7 +3699,7 @@
   [(set_attr "type" "integer")])
 
 (define_expand "bcd<bcd_add_sub>_<code>"
-  [(parallel [(set (reg:CCFP 74)
+  [(parallel [(set (reg:CCFP CR6_REGNO)
                   (compare:CCFP
                    (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "")
                                  (match_operand:V1TI 2 "register_operand" "")
@@ -3708,7 +3708,7 @@
                    (match_dup 4)))
              (clobber (match_scratch:V1TI 5 ""))])
    (set (match_operand:SI 0 "register_operand" "")
-       (BCD_TEST:SI (reg:CCFP 74)
+       (BCD_TEST:SI (reg:CCFP CR6_REGNO)
                     (const_int 0)))]
   "TARGET_P8_VECTOR"
 {
@@ -3727,8 +3727,8 @@
                                 (match_operand:V1TI 2 "register_operand" "")
                                 (match_operand:QI 3 "const_0_to_1_operand" "")]
                                UNSPEC_BCD_ADD_SUB))
-             (clobber (reg:CCFP 74))])
-   (parallel [(set (reg:CCFP 74)
+             (clobber (reg:CCFP CR6_REGNO))])
+   (parallel [(set (reg:CCFP CR6_REGNO)
                   (compare:CCFP
                    (unspec:V2DF [(match_dup 1)
                                  (match_dup 2)
@@ -3742,7 +3742,7 @@
                                 (match_dup 2)
                                 (match_dup 3)]
                                UNSPEC_BCD_ADD_SUB))
-             (set (reg:CCFP 74)
+             (set (reg:CCFP CR6_REGNO)
                   (compare:CCFP
                    (unspec:V2DF [(match_dup 1)
                                  (match_dup 2)
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index fbfa9bf12e4722dd593eea70a31a3b91c6b6a069..d42de0f9d3c05b271390b4cc150afff473f8173a 100644 (file)
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -670,7 +670,7 @@
 ;; setting CR6 to indicate a combined status
 (define_expand "vector_eq_<mode>_p"
   [(parallel
-    [(set (reg:CC 74)
+    [(set (reg:CC CR6_REGNO)
          (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "")
                             (match_operand:VEC_A 2 "vlogical_operand" ""))]
                     UNSPEC_PREDICATE))
@@ -682,7 +682,7 @@
 
 (define_expand "vector_gt_<mode>_p"
   [(parallel
-    [(set (reg:CC 74)
+    [(set (reg:CC CR6_REGNO)
          (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "")
                             (match_operand:VEC_A 2 "vlogical_operand" ""))]
                     UNSPEC_PREDICATE))
@@ -694,7 +694,7 @@
 
 (define_expand "vector_ge_<mode>_p"
   [(parallel
-    [(set (reg:CC 74)
+    [(set (reg:CC CR6_REGNO)
          (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "")
                             (match_operand:VEC_F 2 "vfloat_operand" ""))]
                     UNSPEC_PREDICATE))
@@ -706,7 +706,7 @@
 
 (define_expand "vector_gtu_<mode>_p"
   [(parallel
-    [(set (reg:CC 74)
+    [(set (reg:CC CR6_REGNO)
          (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "")
                              (match_operand:VEC_I 2 "vint_operand" ""))]
                     UNSPEC_PREDICATE))
@@ -720,14 +720,14 @@
 
 (define_expand "cr6_test_for_zero"
   [(set (match_operand:SI 0 "register_operand" "=r")
-       (eq:SI (reg:CC 74)
+       (eq:SI (reg:CC CR6_REGNO)
               (const_int 0)))]
   "TARGET_ALTIVEC || TARGET_VSX"
   "")
 
 (define_expand "cr6_test_for_zero_reverse"
   [(set (match_operand:SI 0 "register_operand" "=r")
-       (eq:SI (reg:CC 74)
+       (eq:SI (reg:CC CR6_REGNO)
               (const_int 0)))
    (set (match_dup 0)
        (xor:SI (match_dup 0)
@@ -737,14 +737,14 @@
 
 (define_expand "cr6_test_for_lt"
   [(set (match_operand:SI 0 "register_operand" "=r")
-       (lt:SI (reg:CC 74)
+       (lt:SI (reg:CC CR6_REGNO)
               (const_int 0)))]
   "TARGET_ALTIVEC || TARGET_VSX"
   "")
 
 (define_expand "cr6_test_for_lt_reverse"
   [(set (match_operand:SI 0 "register_operand" "=r")
-       (lt:SI (reg:CC 74)
+       (lt:SI (reg:CC CR6_REGNO)
               (const_int 0)))
    (set (match_dup 0)
        (xor:SI (match_dup 0)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 60917c541c727afa7673640ca8fb7b7c95563338..359e424d6b4a7684b864e3b333dbed60d8eb01fb 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1499,7 +1499,7 @@
 ;; Compare vectors producing a vector result and a predicate, setting CR6 to
 ;; indicate a combined status
 (define_insn "*vsx_eq_<mode>_p"
-  [(set (reg:CC 74)
+  [(set (reg:CC CR6_REGNO)
        (unspec:CC
         [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
                 (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
@@ -1512,7 +1512,7 @@
   [(set_attr "type" "<VStype_simple>")])
 
 (define_insn "*vsx_gt_<mode>_p"
-  [(set (reg:CC 74)
+  [(set (reg:CC CR6_REGNO)
        (unspec:CC
         [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
                 (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
@@ -1525,7 +1525,7 @@
   [(set_attr "type" "<VStype_simple>")])
 
 (define_insn "*vsx_ge_<mode>_p"
-  [(set (reg:CC 74)
+  [(set (reg:CC CR6_REGNO)
        (unspec:CC
         [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
                 (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]