* m10300-opc.c (lsr_add): Fix typo for "lsr_add imm,reg,reg,reg" case.

pr17742

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c9c73019bf67356b77ae98357082db54ef417e69..cfc56c55ce393b9e47fb0a7748e6b726444aa2c6 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+Mon Oct 12 10:43:51 1998  Jeffrey A Law  (law@cygnus.com)
+
+       * m10300-opc.c (lsr_add): Fix typo for "lsr_add imm,reg,reg,reg" case.
+
 Fri Oct  9 14:01:56 1998  Doug Evans  <devans@seba.cygnus.com>
 
        * m32r-opc.h,m32r-opc.c: Regenerate.

diff --git a/opcodes/m10300-opc.c b/opcodes/m10300-opc.c
index 3d204fa999df5dd9d4e1da32f2d86daa60cacca2..b8c8c62e72cee685ce6ee5a84c83a0e36e3eddff 100644 (file)
--- a/opcodes/m10300-opc.c
+++ b/opcodes/m10300-opc.c
@@ -1480,7 +1480,7 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "cmp_xor",   0xf74a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
 { "cmp_xor",   0xf75a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
 { "lsr_add",   0xf7a00000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
-{ "lsr_add",   0xf7900000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
+{ "lsr_add",   0xf7b00000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
 { "lsr_add",   0xf7a40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
 { "lsr_add",   0xf7b40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
 { "lsr_and",   0xf7a80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},