(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index 768b4d570b3b3bfb670b1b7bb2ef7f7567106e63..266cade27ec1d3089cf359c08063e98a2b6edc13 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -95,7 +95,7 @@ Some examples on different operation widths:
 
 Mode types:
 
-* **predicate zeroing** (sz, dz) if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.
+* **sz dz predicate zeroing**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.
 * **ffirst** or data-dependent fail-on-first: see separate section.
 * **sat mode** or saturation: clamps the result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping.
 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero.  When Rc=1 the CR element (CR0) however is still stored in the CR regfile.  This scheme does not apply to crops (crand, cror).