Change sync controls to async.

diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v
index 05e68caf7e91a6d02759be09648055a44b26025f..09dc36001ffb80a4bf855402de1e754c1f791fd9 100644 (file)
--- a/tests/ice40/adffs.v
+++ b/tests/ice40/adffs.v
@@ -27,7 +27,7 @@ module dffs
     initial begin
       q = 0;
     end
-       always @( posedge clk )
+       always @( posedge clk, posedge pre )
                if ( pre )
                        q <= 1'b1;
                else
@@ -39,9 +39,9 @@ module ndffnr
     initial begin
       q = 0;
     end
-       always @( negedge clk )
-               if ( !clr )
-                       q <= 1'b0;
+       always @( negedge clk, negedge pre )
+               if ( !pre )
+                       q <= 1'b1;
                else
             q <= d;
 endmodule

diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
index f82da6b145cb494d1d327592b3dcbf799b028c6e..548060b665d7bcda9758e6727cc0251d99aefd79 100644 (file)
--- a/tests/ice40/adffs.ys
+++ b/tests/ice40/adffs.ys
@@ -4,8 +4,8 @@ flatten
 equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFFNSR
+select -assert-count 1 t:SB_DFFNS
 select -assert-count 2 t:SB_DFFR
-select -assert-count 1 t:SB_DFFSS
-select -assert-count 1 t:SB_LUT4
-select -assert-none t:SB_DFFNSR t:SB_DFFR t:SB_DFFSS t:SB_LUT4 %% t:* %D
+select -assert-count 1 t:SB_DFFS
+select -assert-count 2 t:SB_LUT4
+select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D