test: fix broken tests.

diff --git a/lambdasoc/test/test_cores_litedram.py b/lambdasoc/test/test_cores_litedram.py
index d58957ce6a09a42cbacf77bf31c1905bb9990c46..64b646471f62c8b2ab18ff115773d4526d61a09a 100644 (file)
--- a/lambdasoc/test/test_cores_litedram.py
+++ b/lambdasoc/test/test_cores_litedram.py
@@ -55,8 +55,8 @@ class ConfigTestCase(unittest.TestCase):
 
     def test_wrong_memtype(self):
         with self.assertRaisesRegex(ValueError,
-                r"Unsupported DRAM type, must be one of \"DDR2\", \"DDR3\" or \"DDR4\", "
-                r"not 'foo'"):
+                r"Unsupported DRAM type, must be one of \"SDR\", \"DDR\", \"LPDDR\", \"DDR2\", "
+                r"\"DDR3\" or \"DDR4\", not 'foo'"):
             cfg = DummyConfig(
                 memtype        = "foo",
                 module_name    = "MT41K256M16",
@@ -424,12 +424,6 @@ class CoreTestCase(unittest.TestCase):
         self.assertEqual(core.user_port.memory_map.addr_width, 29)
         self.assertEqual(core.user_port.memory_map.data_width, 8)
 
-    def test_name_force(self):
-        core_1 = litedram.Core(self._cfg, name="core")
-        core_2 = litedram.Core(self._cfg, name="core", name_force=True)
-        self.assertEqual(core_1.name, "core")
-        self.assertEqual(core_2.name, "core")
-
     def test_ctrl_bus_not_ready(self):
         core = litedram.Core(self._cfg)
         with self.assertRaisesRegex(AttributeError,

diff --git a/lambdasoc/test/test_periph_base.py b/lambdasoc/test/test_periph_base.py
index abd4125231eef6d8898b22c7d39a58102e37f0f6..be18e86368aa92bd5a8d10c956b4cd2b1d99f86e 100644 (file)
--- a/lambdasoc/test/test_periph_base.py
+++ b/lambdasoc/test/test_periph_base.py
@@ -4,6 +4,8 @@ import unittest
 from nmigen import *
 from nmigen.back.pysim import *
 
+from nmigen_soc.memory import MemoryMap
+
 from .utils.wishbone import *
 from ..periph.base import Peripheral, CSRBank, PeripheralBridge
 
@@ -86,10 +88,14 @@ class PeripheralTestCase(unittest.TestCase):
 
 
 class CSRBankTestCase(unittest.TestCase):
-    def test_csr_name(self):
-        bank = CSRBank(name_prefix="foo")
-        bar = bank.csr(1, "r")
-        self.assertEqual(bar.name, "foo_bar")
+    def test_bank_name(self):
+        bank = CSRBank(name="foo")
+        self.assertEqual(bank.name, "foo")
+
+    def test_bank_name_wrong(self):
+        with self.assertRaisesRegex(TypeError,
+                r"Name must be a string, not 2"):
+            bank = CSRBank(name=2)
 
     def test_csr_name_wrong(self):
         bank = CSRBank()
@@ -126,6 +132,8 @@ class PeripheralSimulationTestCase(unittest.TestCase):
 
                 self.win_0   = self.window(addr_width=1, data_width=8, sparse=True, addr=0x000)
                 self.win_1   = self.window(addr_width=1, data_width=32, granularity=8, addr=0x200)
+                self.win_0.memory_map = MemoryMap(addr_width=1, data_width=8)
+                self.win_1.memory_map = MemoryMap(addr_width=3, data_width=8)
 
                 self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
                 self.bus     = self._bridge.bus

diff --git a/lambdasoc/test/test_periph_serial.py b/lambdasoc/test/test_periph_serial.py
index 971593a351c24abc90ff21e5f8c9a3fbd5e2e2d2..e84ff3ea4b4753b678c41aac32bfb42e6f2f004e 100644 (file)
--- a/lambdasoc/test/test_periph_serial.py
+++ b/lambdasoc/test/test_periph_serial.py
@@ -4,6 +4,8 @@ from nmigen import *
 from nmigen.lib.io import pin_layout
 from nmigen.back.pysim import *
 
+from nmigen_stdio.serial import AsyncSerial
+
 from .utils.wishbone import *
 from ..periph.serial import AsyncSerialPeripheral
 
@@ -23,7 +25,9 @@ class AsyncSerialPeripheralTestCase(unittest.TestCase):
     def test_loopback(self):
         pins = Record([("rx", pin_layout(1, dir="i")),
                        ("tx", pin_layout(1, dir="o"))])
-        dut = AsyncSerialPeripheral(divisor=5, pins=pins)
+
+        core = AsyncSerial(divisor=5, pins=pins)
+        dut = AsyncSerialPeripheral(core=core)
         m = Module()
         m.submodules.serial = dut
         m.d.comb += pins.rx.i.eq(pins.tx.o)