Merge pull request #154 from daveshah1/yosys_xilinx_edif

build/xilinx: Update Yosys write_edif parameters

diff --git a/litex/build/lattice/trellis.py b/litex/build/lattice/trellis.py
index f4c7c05cfcd24480e327d5325d0051b7f25b2348..63a8d75d4a0c5f96e9cfae2fe62bccfa4e894a6c 100644 (file)
--- a/litex/build/lattice/trellis.py
+++ b/litex/build/lattice/trellis.py
@@ -143,7 +143,7 @@ class LatticeTrellisToolchain:
         self.build_template = [
             "yosys -q -l {build_name}.rpt {build_name}.ys",
             "nextpnr-ecp5 --json {build_name}.json --lpf {build_name}.lpf --textcfg {build_name}.config --{architecture} --package {package} --freq {freq_constraint}",
-            "ecppack {build_name}.config {build_name}.bit"
+            "ecppack {build_name}.config --svf {build_name}.svf --bit {build_name}.bit"
         ]
 
         self.freq_constraints = dict()

diff --git a/litex/build/microsemi/libero_soc.py b/litex/build/microsemi/libero_soc.py
index 4327f62393c28e5797654aa0b2b3d8f5e5f0e86c..a82ac5862615962617138b69bbe6e3af7931c237 100644 (file)
--- a/litex/build/microsemi/libero_soc.py
+++ b/litex/build/microsemi/libero_soc.py
@@ -23,6 +23,8 @@ def _format_io_constraint(c):
     elif isinstance(c, IOStandard):
         return "-io_std {} ".format(c.name)
     elif isinstance(c, Misc):
+        return "-RES_PULL {} ".format(c.misc)
+    else:
         raise NotImplementedError
 
 
@@ -183,7 +185,10 @@ def _build_script(build_name, device, toolchain_path, ver=None):
         copy_stmt = "copy"
         fail_stmt = " || exit /b"
     else:
-        raise NotImplementedError
+        script_ext = ".sh"
+        build_script_contents = "# Autogenerated by Migen\n\n"
+        copy_stmt = "cp"
+        fail_stmt = " || exit 1"
 
     build_script_file = "build_" + build_name + script_ext
     tools.write_to_file(build_script_file, build_script_contents,

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 1edcc3f7bba90c376b50aef7d8a4fb225a7ecf6e..5a1afedcbde95f62813a0c65d7887653bbc2758e 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -18,6 +18,9 @@ class VexRiscv(Module, AutoCSR):
         variant = "std_debug" if variant == "debug" else variant
         variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug")
         assert variant in variants, "Unsupported variant %s" % variant
+        self.platform = platform
+        self.variant = variant
+        self.external_variant = None
         self.reset = Signal()
         self.ibus = ibus = wishbone.Interface()
         self.dbus = dbus = wishbone.Interface()
@@ -59,9 +62,6 @@ class VexRiscv(Module, AutoCSR):
         if "debug" in variant:
             self.add_debug()
 
-        # add verilog sources
-        self.add_sources(platform, variant)
-
     def add_debug(self):
         debug_reset = Signal()
 
@@ -155,12 +155,18 @@ class VexRiscv(Module, AutoCSR):
             "std_debug":  "VexRiscv_Debug.v",
             "lite":       "VexRiscv_Lite.v",
             "lite_debug": "VexRiscv_LiteDebug.v",
-            "min":        "VexRiscv_Lite.v",
-            "min_debug":  "VexRiscv_LiteDebug.v",
+            "min":        "VexRiscv_Min.v",
+            "min_debug":  "VexRiscv_MinDebug.v",
         }
         cpu_filename = verilog_variants[variant]
         vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
         platform.add_source(os.path.join(vdir, cpu_filename))
 
+    def use_external_variant(self, variant_filename):
+        self.external_variant = True
+        self.platform.add_source(variant_filename)
+
     def do_finalize(self):
+        if not self.external_variant:
+            self.add_sources(self.platform, self.variant)
         self.specials += Instance("VexRiscv", **self.cpu_params)

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index ed9c02af056f934a69acfea29b4f7ab1db434ba2..b8897d00b53fe8ce8abedbbdae90537f37aa0933 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -1,5 +1,7 @@
+import os
 import struct
 import inspect
+import json
 from operator import itemgetter
 
 from migen import *
@@ -36,25 +38,44 @@ def mem_decoder(address, start=26, end=29):
 
 
 def get_mem_data(filename, endianness="big", mem_size=None):
-    data = []
-    with open(filename, "rb") as mem_file:
-        while True:
-            w = mem_file.read(4)
-            if not w:
-                break
-            if endianness == "little":
-                data.append(struct.unpack("<I", w)[0])
-            else:
-                data.append(struct.unpack(">I", w)[0])
-    data_size = len(data)*4
+    # create memory regions
+    _, ext = os.path.splitext(filename)
+    if ext == ".json":
+        f = open(filename, "r")
+        regions = json.load(f)
+        f.close()
+    else:
+        regions = {filename: "0x00000000"}
+
+    # determine data_size
+    data_size = 0
+    for filename, base in regions.items():
+        data_size = max(int(base, 16) + os.path.getsize(filename), data_size)
     assert data_size > 0
     if mem_size is not None:
         assert data_size < mem_size, (
             "file is too big: {}/{} bytes".format(
-                data_size, mem_size))
+             data_size, mem_size))
+
+    # fill data
+    data = [0]*(data_size//4)
+    for filename, base in regions.items():
+        with open(filename, "rb") as f:
+            i = 0
+            while True:
+                w = f.read(4)
+                if not w:
+                    break
+                if len(w) != 4:
+                    for i in range(len(w), 4):
+                        w += b'\x00'
+                if endianness == "little":
+                    data[i] = struct.unpack("<I", w)[0]
+                else:
+                    data[i] = struct.unpack(">I", w)[0]
+                i += 1
     return data
 
-
 class ReadOnlyDict(dict):
     def __readonly__(self, *args, **kwargs):
         raise RuntimeError("Cannot modify ReadOnlyDict")

diff --git a/litex/utils/__init__.py b/litex/utils/__init__.py
new file mode 100644 (file)
index 0000000..8b13789
--- /dev/null
+++ b/litex/utils/__init__.py
@@ -0,0 +1 @@
+

diff --git a/litex/utils/litex_sim.py b/litex/utils/litex_sim.py
index 4e6eb88dc289ed6e8efb4d8a2b4192206b5bc732..808bd8b9bdef9ee44ba720af7478425435794cce 100755 (executable)
--- a/litex/utils/litex_sim.py
+++ b/litex/utils/litex_sim.py
@@ -215,14 +215,20 @@ def main():
 
     sim_config = SimConfig(default_clk="sys_clk")
     sim_config.add_module("serial2console", "serial")
+
+    cpu_endianness = "big"
+    if "cpu_type" in soc_kwargs:
+        if soc_kwargs["cpu_type"] in ["picorv32", "vexriscv"]:
+            cpu_endianness = "little"
+
     if args.rom_init:
-        soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init)
+        soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
     if not args.with_sdram:
-        soc_kwargs["integrated_main_ram_size"] = 0x10000
+        soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
         if args.ram_init is not None:
-            soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init)
-            soc_kwargs["integrated_main_ram_size"] = max(len(soc_kwargs["integrated_main_ram_init"]), 0x10000)
+            soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu_endianness)
     else:
+        assert args.ram_init is None
         soc_kwargs["integrated_main_ram_size"] = 0x0
     if args.with_ethernet:
         sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
@@ -235,6 +241,8 @@ def main():
         with_etherbone=args.with_etherbone,
         with_analyzer=args.with_analyzer,
         **soc_kwargs)
+    if args.ram_init is not None:
+        soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
     builder_kwargs["csr_csv"] = "csr.csv"
     builder = Builder(soc, **builder_kwargs)
     vns = builder.build(run=False, threads=args.threads, sim_config=sim_config, trace=args.trace)