self.build_template = [
"yosys -q -l {build_name}.rpt {build_name}.ys",
"nextpnr-ecp5 --json {build_name}.json --lpf {build_name}.lpf --textcfg {build_name}.config --{architecture} --package {package} --freq {freq_constraint}",
- "ecppack {build_name}.config {build_name}.bit"
+ "ecppack {build_name}.config --svf {build_name}.svf --bit {build_name}.bit"
]
self.freq_constraints = dict()
elif isinstance(c, IOStandard):
return "-io_std {} ".format(c.name)
elif isinstance(c, Misc):
+ return "-RES_PULL {} ".format(c.misc)
+ else:
raise NotImplementedError
copy_stmt = "copy"
fail_stmt = " || exit /b"
else:
- raise NotImplementedError
+ script_ext = ".sh"
+ build_script_contents = "# Autogenerated by Migen\n\n"
+ copy_stmt = "cp"
+ fail_stmt = " || exit 1"
build_script_file = "build_" + build_name + script_ext
tools.write_to_file(build_script_file, build_script_contents,
variant = "std_debug" if variant == "debug" else variant
variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug")
assert variant in variants, "Unsupported variant %s" % variant
+ self.platform = platform
+ self.variant = variant
+ self.external_variant = None
self.reset = Signal()
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
if "debug" in variant:
self.add_debug()
- # add verilog sources
- self.add_sources(platform, variant)
-
def add_debug(self):
debug_reset = Signal()
"std_debug": "VexRiscv_Debug.v",
"lite": "VexRiscv_Lite.v",
"lite_debug": "VexRiscv_LiteDebug.v",
- "min": "VexRiscv_Lite.v",
- "min_debug": "VexRiscv_LiteDebug.v",
+ "min": "VexRiscv_Min.v",
+ "min_debug": "VexRiscv_MinDebug.v",
}
cpu_filename = verilog_variants[variant]
vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_source(os.path.join(vdir, cpu_filename))
+ def use_external_variant(self, variant_filename):
+ self.external_variant = True
+ self.platform.add_source(variant_filename)
+
def do_finalize(self):
+ if not self.external_variant:
+ self.add_sources(self.platform, self.variant)
self.specials += Instance("VexRiscv", **self.cpu_params)
+import os
import struct
import inspect
+import json
from operator import itemgetter
from migen import *
def get_mem_data(filename, endianness="big", mem_size=None):
- data = []
- with open(filename, "rb") as mem_file:
- while True:
- w = mem_file.read(4)
- if not w:
- break
- if endianness == "little":
- data.append(struct.unpack("<I", w)[0])
- else:
- data.append(struct.unpack(">I", w)[0])
- data_size = len(data)*4
+ # create memory regions
+ _, ext = os.path.splitext(filename)
+ if ext == ".json":
+ f = open(filename, "r")
+ regions = json.load(f)
+ f.close()
+ else:
+ regions = {filename: "0x00000000"}
+
+ # determine data_size
+ data_size = 0
+ for filename, base in regions.items():
+ data_size = max(int(base, 16) + os.path.getsize(filename), data_size)
assert data_size > 0
if mem_size is not None:
assert data_size < mem_size, (
"file is too big: {}/{} bytes".format(
- data_size, mem_size))
+ data_size, mem_size))
+
+ # fill data
+ data = [0]*(data_size//4)
+ for filename, base in regions.items():
+ with open(filename, "rb") as f:
+ i = 0
+ while True:
+ w = f.read(4)
+ if not w:
+ break
+ if len(w) != 4:
+ for i in range(len(w), 4):
+ w += b'\x00'
+ if endianness == "little":
+ data[i] = struct.unpack("<I", w)[0]
+ else:
+ data[i] = struct.unpack(">I", w)[0]
+ i += 1
return data
-
class ReadOnlyDict(dict):
def __readonly__(self, *args, **kwargs):
raise RuntimeError("Cannot modify ReadOnlyDict")
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
+
+ cpu_endianness = "big"
+ if "cpu_type" in soc_kwargs:
+ if soc_kwargs["cpu_type"] in ["picorv32", "vexriscv"]:
+ cpu_endianness = "little"
+
if args.rom_init:
- soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init)
+ soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
if not args.with_sdram:
- soc_kwargs["integrated_main_ram_size"] = 0x10000
+ soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
- soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init)
- soc_kwargs["integrated_main_ram_size"] = max(len(soc_kwargs["integrated_main_ram_init"]), 0x10000)
+ soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu_endianness)
else:
+ assert args.ram_init is None
soc_kwargs["integrated_main_ram_size"] = 0x0
if args.with_ethernet:
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
with_etherbone=args.with_etherbone,
with_analyzer=args.with_analyzer,
**soc_kwargs)
+ if args.ram_init is not None:
+ soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
vns = builder.build(run=False, threads=args.threads, sim_config=sim_config, trace=args.trace)