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Merge pull request #154 from daveshah1/yosys_xilinx_edif
author
enjoy-digital
<florent@enjoy-digital.fr>
Fri, 22 Mar 2019 16:43:40 +0000
(17:43 +0100)
committer
GitHub
<noreply@github.com>
Fri, 22 Mar 2019 16:43:40 +0000
(17:43 +0100)
build/xilinx: Update Yosys write_edif parameters
litex/build/xilinx/common.py
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diff --git
a/litex/build/xilinx/common.py
b/litex/build/xilinx/common.py
index da22e635815f853591f829264e224f8f334acdbc..36da5b66ecab4decd8b186825876fbce01675acb 100644
(file)
--- a/
litex/build/xilinx/common.py
+++ b/
litex/build/xilinx/common.py
@@
-265,7
+265,7
@@
setattr -set keep 1 a:async_reg=true
synth_xilinx -top top
-write_edif -attrprop {build_name}.edif
+write_edif -
pvector bra -
attrprop {build_name}.edif
""".format(build_name=build_name)
ys_name = build_name + ".ys"