Merge pull request #154 from daveshah1/yosys_xilinx_edif

build/xilinx: Update Yosys write_edif parameters

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
index da22e635815f853591f829264e224f8f334acdbc..36da5b66ecab4decd8b186825876fbce01675acb 100644 (file)
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@@ -265,7 +265,7 @@ setattr -set keep 1 a:async_reg=true
 
 synth_xilinx -top top
 
-write_edif -attrprop {build_name}.edif
+write_edif -pvector bra -attrprop {build_name}.edif
 """.format(build_name=build_name)
 
     ys_name = build_name + ".ys"