rl78.h (enum reg_class): Remove real registers from General register class.
authorNick Clifton <nickc@redhat.com>
Wed, 4 Mar 2015 14:54:15 +0000 (14:54 +0000)
committerNick Clifton <nickc@gcc.gnu.org>
Wed, 4 Mar 2015 14:54:15 +0000 (14:54 +0000)
* config/rl78/rl78.h (enum reg_class): Remove real registers from
General register class.
* config/rl78/rl78-real.md: Replace general register constraints
with real+virtual register constraints.

From-SVN: r221185

gcc/ChangeLog
gcc/config/rl78/rl78-real.md
gcc/config/rl78/rl78.h

index 58f421f6398c5e02f93b26efba5a61dc10cab0af..27c712b14533560753e48f029249527625f680f5 100644 (file)
@@ -1,3 +1,10 @@
+2015-03-04  Nick Clifton  <nickc@redhat.com>
+
+       * config/rl78/rl78.h (enum reg_class): Remove real registers from
+       General register class.
+       * config/rl78/rl78-real.md: Replace general register constraints
+       with real+virtual register constraints.
+
 2015-03-04  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
        * gcc/config/s390/s390.c (s390_expand_builtin): Exlude non-htm
index cfd9742a5d7090f0d5d83a8b1d401cac41daeddb..f6ab7ff42138b5a02a6ead9e7420c9a3d14c1bba 100644 (file)
@@ -59,7 +59,7 @@
 )
 
 (define_insn "*movqi_real"
-  [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=g,RaxbcWab,RaxbcWab,a,                               bcx,R,     WabWd2WhlWh1WhbWbcWs1v, bcx,WsaWsf")
+  [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=Rv,RaxbcWab,RaxbcWab,a,                               bcx,R,     WabWd2WhlWh1WhbWbcWs1v, bcx,WsaWsf")
        (match_operand    1 "rl78_general_operand"      "0,K,        M,       RInt8sJvWabWdeWd2WhlWh1WhbWbcWs1,Wab,aInt8J,a,                      R,  i"))]
   "rl78_real_insns_ok ()"
   "@
@@ -75,7 +75,7 @@
 )
 
 (define_insn "*movhi_real"
-  [(set (match_operand:HI 0 "rl78_nonimmediate_operand" "=g,AB,AB,RSv,A,BDTvSWabWd2WdeWhlWh1WbcWs1, BDT,ABDT,v")
+  [(set (match_operand:HI 0 "rl78_nonimmediate_operand" "=Rv,AB,AB,RSv,A,BDTvSWabWd2WdeWhlWh1WbcWs1, BDT,ABDT,v")
        (match_operand:HI 1 "rl78_general_operand"      " 0,K, M, i,  BDTvSWabWd2WdeWh1WhlWbcWs1,A, BDT,vS,  ABDT"))]
   "rl78_real_insns_ok ()"
   "@
@@ -93,7 +93,7 @@
 ;;---------- Conversions ------------------------
 
 (define_insn "*zero_extendqihi2_real"
-  [(set (match_operand:HI                 0 "nonimmediate_operand" "=rv,A")
+  [(set (match_operand:HI                 0 "nonimmediate_operand" "=Rv,A")
        (zero_extend:HI (match_operand:QI 1 "general_operand" "0,a")))]
   "rl78_real_insns_ok ()"
   "@
 ;;---------- Arithmetic ------------------------
 
 (define_insn "*addqi3_real"
-  [(set (match_operand:QI          0 "rl78_nonimmediate_operand"  "=rvWabWhlWh1Wsa,rvWabWhlWh1Wsa,a,*bcdehl,Wsa")
+  [(set (match_operand:QI          0 "rl78_nonimmediate_operand"  "=RvWabWhlWh1Wsa,RvWabWhlWh1Wsa,a,*bcdehl,Wsa")
        (plus:QI (match_operand:QI 1 "rl78_general_operand"  "%0,0,0,0,0")
                 (match_operand:QI 2 "rl78_general_operand" "K,L,RWhlWh1Wabi,a,i")))
    ]
 )
 
 (define_insn "*addqihi3a_real"
-  [(set (match_operand:HI                          0 "register_operand" "=r")
-       (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand"  "r"))
+  [(set (match_operand:HI                          0 "register_operand" "=R")
+       (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand"  "R"))
                 (match_operand:HI                 2 "register_operand"  "0")))
    ]
   "rl78_real_insns_ok ()"
   [(set (pc) (if_then_else
              (match_operator 0 "rl78_cmp_operator_real"
                              [(match_operand:QI 1 "rl78_general_operand" "Wabvaxbc,a,              vWsaWab,bcdehl")
-                              (match_operand:QI 2 "rl78_general_operand" "M,       irvWabWhlWh1Whb,i,a")])
+                              (match_operand:QI 2 "rl78_general_operand" "M,       iRvWabWhlWh1Whb,i,a")])
               (label_ref (match_operand 3 "" ""))
              (pc)))]
   "rl78_real_insns_ok ()"
index d7ec21c0c8535164f299e314db918078aff6068c..caa7f7f65413698216516947c1293169944689d2 100644 (file)
@@ -266,7 +266,7 @@ enum reg_class
   { 0x00000c00, 0x00000000 },  /* R10 - HImode */              \
   { 0xff000000, 0x00000000 },  /* INT - HImode */              \
   { 0xff7fff00, 0x00000000 },  /* Virtual registers.  */       \
-  { 0xff7fffff, 0x00000002 },  /* General registers.  */       \
+  { 0xff7fff00, 0x00000002 },  /* General registers.  */       \
   { 0x04000000, 0x00000004 },  /* PSW.  */     \
   { 0xff7fffff, 0x0000001f }   /* All registers.  */           \
 }