soc_core: add UART bridge support (simplify having to do it externally)

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 33240ff2b7ff6712fed0f612d7bf1b667d8bb4a0..597b2aa2ba5ee819be74b16a7db983072115da8f 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -243,6 +243,9 @@ class SoCCore(Module):
                 self.submodules.uart = uart.UART()
                 if uart_name == "stub":
                     self.comb += self.uart.sink.ready.eq(1)
+            elif uart_name == "bridge":
+                self.submodules.uart = uart.UARTWishboneBridge(platform.request("serial"), clk_freq, uart_baudrate)
+                self.add_wb_master(self.uart.wishbone)
             elif uart_name == "crossover":
                 self.submodules.uart = uart.UARTCrossover()
             else: