boards/platforms/arty: add spi pins

diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py
index d4c88eae1ee82c7d95d48c70901307ff79d097da..15283ece977858f2f051ae304bfe7be12af8785b 100644 (file)
--- a/litex/boards/platforms/arty.py
+++ b/litex/boards/platforms/arty.py
@@ -37,6 +37,14 @@ _io = [
         Subsignal("rx", Pins("A9")),
         IOStandard("LVCMOS33")),
 
+    ("spi", 0,
+        Subsignal("clk", Pins("F1")),
+        Subsignal("cs_n", Pins("C1")),
+        Subsignal("mosi", Pins("H1")),
+        Subsignal("miso", Pins("G1")),
+        IOStandard("LVCMOS33")
+    ),
+
     ("spiflash_4x", 0,  # clock needs to be accessed through STARTUPE2
         Subsignal("cs_n", Pins("L13")),
         Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
@@ -51,6 +59,7 @@ _io = [
         IOStandard("LVCMOS33")
     ),
 
+
     ("eth_ref_clk", 0, Pins("G18"), IOStandard("LVCMOS33")),
 
     ("ddram", 0,