radeonsi: program the DRAWID SGPR

Note that for indirect draws, the new MULTI firmware packets are required.

There's also no need to reset last_{start_instance,sh_base_reg}, since
resetting last_base_vertex is sufficient.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 9e6bd78711bb5ffe96386a0d4f23757db6a85ef1..f6535cfc8a690dd470c4a75efc3e955cf181df6d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -308,6 +308,7 @@ struct si_context {
        /* Emitted draw state. */
        int                     last_base_vertex;
        int                     last_start_instance;
+       int                     last_drawid;
        int                     last_sh_base_reg;
        int                     last_primitive_restart_en;
        int                     last_restart_index;
@@ -414,8 +415,6 @@ static inline void
 si_invalidate_draw_sh_constants(struct si_context *sctx)
 {
        sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
-       sctx->last_start_instance = -1; /* reset to an unknown value */
-       sctx->last_sh_base_reg = -1; /* reset to an unknown value */
 }
 
 static inline void

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 314731164c9a6cedd26e2d9b5ad6051defe321ee..d518d42b571d57fe05f0db36dac810d6d103fe09 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -591,13 +591,16 @@ static void si_emit_draw_packets(struct si_context *sctx,
                if (base_vertex != sctx->last_base_vertex ||
                    sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
                    info->start_instance != sctx->last_start_instance ||
+                   info->drawid != sctx->last_drawid ||
                    sh_base_reg != sctx->last_sh_base_reg) {
-                       radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
+                       radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
                        radeon_emit(cs, base_vertex);
                        radeon_emit(cs, info->start_instance);
+                       radeon_emit(cs, info->drawid);
 
                        sctx->last_base_vertex = base_vertex;
                        sctx->last_start_instance = info->start_instance;
+                       sctx->last_drawid = info->drawid;
                        sctx->last_sh_base_reg = sh_base_reg;
                }
        } else {
@@ -647,7 +650,8 @@ static void si_emit_draw_packets(struct si_context *sctx,
                        radeon_emit(cs, info->indirect_offset);
                        radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
                        radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
-                       radeon_emit(cs, 0); /* draw_index */
+                       radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
+                                       S_2C3_DRAW_INDEX_ENABLE(1));
                        radeon_emit(cs, 1); /* count */
                        radeon_emit(cs, 0); /* count_addr -- disabled */
                        radeon_emit(cs, 0);