radeonsi: remove useless code that handles dx10_clamp_mode

"enable-no-nans-fp-math" is a wrong string and there was a disagreement
about fixing it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index bd45d4ae8dbecefb790e60ca707ae9f9bbb7bc04..c92f07cff63d45a382108e0781684b6cef068c1f 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3654,10 +3654,6 @@ static void create_function(struct si_shader_context *si_shader_ctx)
        radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
        radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
 
-       if (shader->dx10_clamp_mode)
-               LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
-                                                  "enable-no-nans-fp-math", "true");
-
        for (i = 0; i <= last_sgpr; ++i) {
                LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
 
@@ -4341,9 +4337,6 @@ int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
        si_init_shader_ctx(&si_shader_ctx, sscreen, shader, tm,
                           poly_stipple ? &stipple_shader_info : &sel->info);
 
-       if (sel->type != PIPE_SHADER_COMPUTE)
-               shader->dx10_clamp_mode = true;
-
        shader->uses_instanceid = sel->info.uses_instanceid;
 
        bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;

diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h
index 04b977af943f5fbb67c3c0de1b3e601bf688e5c5..e3d1f4f39a1789b193034b66c4fc4d8ea4460340 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -283,7 +283,6 @@ struct si_shader {
        bool                    uses_instanceid;
        unsigned                nr_pos_exports;
        unsigned                nr_param_exports;
-       bool                    dx10_clamp_mode; /* convert NaNs to 0 */
 };
 
 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 6e656b07ca1a576a6aae8b39d274d5d195dd8fcb..f48d7ca360fd493eb794b59f574ee971b2481b90 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -124,7 +124,7 @@ static void si_shader_ls(struct si_shader *shader)
        shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
                           S_00B528_SGPRS((num_sgprs - 1) / 8) |
                           S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
-                          S_00B528_DX10_CLAMP(shader->dx10_clamp_mode);
+                          S_00B528_DX10_CLAMP(1);
        shader->config.rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
                           S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
 }
@@ -157,7 +157,7 @@ static void si_shader_hs(struct si_shader *shader)
        si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
                       S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
                       S_00B428_SGPRS((num_sgprs - 1) / 8) |
-                      S_00B428_DX10_CLAMP(shader->dx10_clamp_mode));
+                      S_00B428_DX10_CLAMP(1));
        si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
                       S_00B42C_USER_SGPR(num_user_sgprs) |
                       S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
@@ -203,7 +203,7 @@ static void si_shader_es(struct si_shader *shader)
                       S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
                       S_00B328_SGPRS((num_sgprs - 1) / 8) |
                       S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
-                      S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
+                      S_00B328_DX10_CLAMP(1));
        si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
                       S_00B32C_USER_SGPR(num_user_sgprs) |
                       S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
@@ -292,7 +292,7 @@ static void si_shader_gs(struct si_shader *shader)
        si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
                       S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
                       S_00B228_SGPRS((num_sgprs - 1) / 8) |
-                      S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
+                      S_00B228_DX10_CLAMP(1));
        si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
                       S_00B22C_USER_SGPR(num_user_sgprs) |
                       S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
@@ -381,7 +381,7 @@ static void si_shader_vs(struct si_shader *shader, struct si_shader *gs)
                       S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
                       S_00B128_SGPRS((num_sgprs - 1) / 8) |
                       S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
-                      S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
+                      S_00B128_DX10_CLAMP(1));
        si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
                       S_00B12C_USER_SGPR(num_user_sgprs) |
                       S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
@@ -567,7 +567,7 @@ static void si_shader_ps(struct si_shader *shader)
        si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
                       S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
                       S_00B028_SGPRS((num_sgprs - 1) / 8) |
-                      S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
+                      S_00B028_DX10_CLAMP(1));
        si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
                       S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
                       S_00B02C_USER_SGPR(num_user_sgprs) |