ARM: Fix PC operand handling.

diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index e0d2689797092f5334b851e8abb16b34c7f21c00..59d7fe70598ca47d7c5bd0c3cc0f2df50a84e64c 100644 (file)
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -139,6 +139,18 @@ class ArmStaticInstBase : public StaticInst
         return ((spsr & ~bitMask) | (val & bitMask));
     }
 
+    template<class XC>
+    static Addr
+    readPC(XC *xc)
+    {
+        Addr pc = xc->readPC();
+        Addr tBit = pc & (ULL(1) << PcTBitShift);
+        if (tBit)
+            return pc + 4;
+        else
+            return pc + 8;
+    }
+
     template<class XC>
     static void
     setNextPC(XC *xc, Addr val)

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 244d217ce780a969a03e91d3daaa173ddaef148f..911f0425e4784530592b7d727d7908e5836d8031 100644 (file)
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -53,7 +53,7 @@ def operand_types {{
 
 let {{
     maybePCRead = '''
-        ((%(reg_idx)s == PCReg) ? ((xc->readPC() & ~PcModeMask) + 8) :
+        ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
          xc->%(func)s(this, %(op_idx)s))
     '''
     maybePCWrite = '''
@@ -61,9 +61,6 @@ let {{
          xc->%(func)s(this, %(op_idx)s, %(final_val)s))
     '''
 
-    readPC = 'xc->readPC() & ~PcModeMask'
-    writePC = 'setPC(xc, %(final_val)s)'
-
     readNPC = 'xc->readNextPC() & ~PcModeMask'
     writeNPC = 'setNextPC(xc, %(final_val)s)'
 }};
@@ -117,8 +114,6 @@ def operands {{
     'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
     'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
     'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
-    'PC':  ('PC', 'ud', None, (None, None, 'IsControl'), 50,
-            readPC, writePC),
     'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
             readNPC, writeNPC),
 }};