arm: Fix timing wakeup with LLSC
authorAli Saidi <ali.saidi@arm.com>
Wed, 12 Nov 2014 14:05:22 +0000 (09:05 -0500)
committerAli Saidi <ali.saidi@arm.com>
Wed, 12 Nov 2014 14:05:22 +0000 (09:05 -0500)
src/cpu/simple/timing.cc

index 5bfc9799da7f816ace89a9ab5f3b766f0bdfd9a5..2d0ab330e4e26545f4895c5eeccb6abdf158be94 100644 (file)
@@ -243,6 +243,12 @@ bool
 TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
 {
     RequestPtr req = pkt->req;
+
+    // We're about the issues a locked load, so tell the monitor
+    // to start caring about this address
+    if (pkt->isRead() && pkt->req->isLLSC()) {
+        TheISA::handleLockedRead(thread, pkt->req);
+    }
     if (req->isMmappedIpr()) {
         Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
         new IprEvent(pkt, this, clockEdge(delay));
@@ -792,12 +798,6 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
         traceData = NULL;
     }
 
-    // the locked flag may be cleared on the response packet, so check
-    // pkt->req and not pkt to see if it was a load-locked
-    if (pkt->isRead() && pkt->req->isLLSC()) {
-        TheISA::handleLockedRead(thread, pkt->req);
-    }
-
     delete pkt->req;
     delete pkt;