compat.sim: match clock period.

diff --git a/nmigen/compat/sim/__init__.py b/nmigen/compat/sim/__init__.py
index c2a7c7b10cca8995672d6aa97df83ae20f945d0e..4ee04549442d2cb60d5dd1bfe07a97a816ee282f 100644 (file)
--- a/nmigen/compat/sim/__init__.py
+++ b/nmigen/compat/sim/__init__.py
@@ -18,7 +18,7 @@ def run_simulation(fragment_or_module, generators, clocks={"sync": 10}, vcd_name
 
     with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim:
         for domain, period in clocks.items():
-            sim.add_clock(period, domain)
+            sim.add_clock(period / 1e9, domain)
         for domain, process in generators.items():
             sim.add_sync_process(process, domain)
         sim.run()