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diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 56441bd3742c4798b385231689ba7d92d4e17c06..c5d40949f95f8b2691d628923b855462bf8b606c 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -32,28 +32,40 @@ defined in the Prefix Fields section.
 
 ## MASK Encoding
 
-TODO: split out (remove) bit 3 as separate so that twin predication can use the same encoding, and split the table into 2 halves. The bit currently 3 becomes a separate (standalone) field (see [discussion]) that selects *both* src and dest predication as CR based or both as INT based.  This saves one bit and makes things less complex to implement in hardware.
-
-Integer based predication.  Twin predication uses the same encoding thus allowing either the same register (r3 or r10) to be used for both src and dest, or different regs (one for src, one for dest)
-
-| Value | Mnemonic          | Description                                            |
-|-------|-------------------|--------------------------------------------------------|
-| 0000  | -                 | Reserved (causes an illegal instruction trap)          |
-| 0001  | ALWAYS (implicit) | Operation is not masked  see [[discussion]]            |
-| 0010  | R3                | Element `i` is enabled if `R3 & (1 << i)` is non-zero  |
-| 0011  | ~R3               | Element `i` is enabled if `R3 & (1 << i)` is zero      |
-| 0100  | R10               | Element `i` is enabled if `R10 & (1 << i)` is non-zero |
-| 0101  | ~R10              | Element `i` is enabled if `R10 & (1 << i)` is zero     |
-| 0110  | R30               | Element `i` is enabled if `R30 & (1 << i)` is non-zero |
-| 0111  | ~R30              | Element `i` is enabled if `R30 & (1 << i)` is zero     |
-| 1000  | lt                | Element `i` is enabled if `CR[6+i].LT` is set          |
-| 1001  | nl/ge             | Element `i` is enabled if `CR[6+i].LT` is clear        |
-| 1010  | gt                | Element `i` is enabled if `CR[6+i].GT` is set          |
-| 1011  | ng/le             | Element `i` is enabled if `CR[6+i].GT` is clear        |
-| 1100  | eq                | Element `i` is enabled if `CR[6+i].EQ` is set          |
-| 1101  | ne                | Element `i` is enabled if `CR[6+i].EQ` is clear        |
-| 1110  | so/un             | Element `i` is enabled if `CR[6+i].FU` is set          |
-| 1111  | ns/nu             | Element `i` is enabled if `CR[6+i].FU` is clear        |
+One bit indicates the mode: CR or Int predication.   The two types may not be mixed.
+
+Twin predication uses the same encoding thus allowing either the same register (r3 or r10) to be used for both src and dest, or different regs (one for src, one for dest).
+
+### Integer Predication
+
+When the predicate mode bit is zero the 3 bits are interpreted as below. 
+Twin predication has an identical 3 bit field similarly encoded.
+
+| Value | Mnemonic | Description                                            |
+|-------|----------|--------------------------------------------------------|
+| 000  | ALWAYS    | Operation is not masked  see [[discussion]]            |
+| 001  | 1 << R3   | Reserved (causes an illegal instruction trap)          |
+| 010  | R3        | Element `i` is enabled if `R3 & (1 << i)` is non-zero  |
+| 011  | ~R3       | Element `i` is enabled if `R3 & (1 << i)` is zero      |
+| 100  | R10       | Element `i` is enabled if `R10 & (1 << i)` is non-zero |
+| 101  | ~R10      | Element `i` is enabled if `R10 & (1 << i)` is zero     |
+| 110  | R30       | Element `i` is enabled if `R30 & (1 << i)` is non-zero |
+| 111  | ~R30      | Element `i` is enabled if `R30 & (1 << i)` is zero     |
+
+### CR based predication
+
+When the predicate mode bit is one the 3 bits are interpreted as below.  Twin predication has an identical 3 bit field similarly encoded
+
+| Value | Mnemonic | Description                                            |
+|-------|----------|--------------------------------------------------------|
+| 000  | lt        | Element `i` is enabled if `CR[6+i].LT` is set          |
+| 001  | nl/ge     | Element `i` is enabled if `CR[6+i].LT` is clear        |
+| 010  | gt        | Element `i` is enabled if `CR[6+i].GT` is set          |
+| 011  | ng/le     | Element `i` is enabled if `CR[6+i].GT` is clear        |
+| 100  | eq        | Element `i` is enabled if `CR[6+i].EQ` is set          |
+| 101  | ne        | Element `i` is enabled if `CR[6+i].EQ` is clear        |
+| 110  | so/un     | Element `i` is enabled if `CR[6+i].FU` is set          |
+| 111  | ns/nu     | Element `i` is enabled if `CR[6+i].FU` is clear        |
 
 CR based predication.  TODO: select alternate CR for twin predication? see [[discussion]]  Overlap of the two CR based predicates must be taken into account, so the starting point for one of them must be suitably high, or accept that for twin predication VL must not exceed the range where overlap will occur, *or* that they use the same starting point but select different *bits* of the same CRs