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diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 7b7ab4b058f8ccaf546da8f1334e9bd32d651bc3..b62be5ca5833b1f3117d0822cdd3f1ca58d44af5 100644 (file)
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -18,6 +18,11 @@ out-enable) to be routed right the way from the ASIC, all
 the way to the IO PAD, where only then does a wire bond connect
 it to a single external pin.
 
+Below, therefore is a (simplified) diagram of what is
+usually contained in an FPGA's bi-directional IO Pad,
+and consequently this is what you must also provide, and explicitly
+wire up in your ASIC's HDL.
+
 [[!img asic_iopad_gen.svg]]
 
 Designing an ASIC, there is no guarantee that the IO pad is