execution pipeline (Alpha trapb & excb).
Add support for write memory barriers (mostly impacts
store buffer).
Add StaticInst flag to indicate memory barriers, though
this is not modeled in the pipeline yet.
arch/alpha/isa_desc:
Implement trapb, excb, mb, and wmb as insts with
no execution effect (empty execute() function) but
with flags that indicate their side effects.
Also make sure every instruction that needs to go to
the execute stage has a real opClass value, since we
are now using No_OpClass to signal insts that can get
dropped at dispatch.
StaticInst::branchTarget() is now a const method.
cpu/static_inst.hh:
Add flags to indicate serializing insts (trapb, excb) and
memory and write barriers.
Also declare some StaticInst methods as const methods.
dev/etherlink.hh:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
Make name() return value const.
--HG--
extra : convert_revision :
39520e71469fa20e0a7446b2e06b494eec17a02c
{
}
- Addr branchTarget(Addr branchPC)
+ Addr branchTarget(Addr branchPC) const
{
return branchPC + 4 + disp;
}
{
}
- Addr branchTarget(ExecContext *xc)
+ Addr branchTarget(ExecContext *xc) const
{
Addr NPC = xc->readPC() + 4;
uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
// miscellaneous mem-format ops
0x18: decode MEMFUNC {
format WarnUnimpl {
- 0x0000: trapb();
- 0x0400: excb();
- 0x4000: mb();
- 0x4400: wmb();
0x8000: fetch();
0xa000: fetch_m();
0xe800: ecb();
format BasicOperate {
0xc000: rpcc({{ Ra = curTick; }});
+
+ // All of the barrier instructions below do nothing in
+ // their execute() methods (hence the empty code blocks).
+ // All of their functionality is hard-coded in the
+ // pipeline based on the flags IsSerializing,
+ // IsMemBarrier, and IsWriteBarrier. In the current
+ // detailed CPU model, the execute() function only gets
+ // called at fetch, so there's no way to generate pipeline
+ // behavior at any other stage. Once we go to an
+ // exec-in-exec CPU model we should be able to get rid of
+ // these flags and implement this behavior via the
+ // execute() methods.
+
+ // trapb is just a barrier on integer traps, where excb is
+ // a barrier on integer and FP traps. "EXCB is thus a
+ // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
+ // them the same though.
+ 0x0000: trapb({{ }}, IsSerializing, No_OpClass);
+ 0x0400: excb({{ }}, IsSerializing, No_OpClass);
+ 0x4000: mb({{ }}, IsMemBarrier);
+ 0x4400: wmb({{ }}, IsWriteBarrier);
}
#ifdef FULL_SYSTEM
if (!xc->misspeculating()) {
xc->regs.intrflag = 0;
}
- }}, No_OpClass);
+ }});
0xf000: rs({{
Ra = xc->regs.intrflag;
if (!xc->misspeculating()) {
xc->regs.intrflag = 1;
}
- }}, No_OpClass);
+ }});
}
#else
format FailUnimpl {
if (!xc->misspeculating())
AlphaPseudo::m5exit(xc);
}}, No_OpClass);
- 0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
+ 0x30: initparam({{ Ra = cpu->system->init_param; }});
0x40: resetstats({{
if (!xc->misspeculating())
AlphaPseudo::resetstats(xc);
/// - If IsControl is set, then exactly one of IsDirectControl or
/// IsIndirect Control will be set, and exactly one of
/// IsCondControl or IsUncondControl will be set.
+ /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
+ /// implemented as flags since in the current model there's no
+ /// other way for instructions to inject behavior into the
+ /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
+ /// model we should be able to get rid of these flags and
+ /// implement this behavior via the execute() methods.
///
enum Flags {
IsNop, ///< Is a no-op (no effect at all).
IsCall, ///< Subroutine call.
IsReturn, ///< Subroutine return.
- IsThreadSync, ///< Thread synchronization operation.
+ IsThreadSync, ///< Thread synchronization operation.
+
+ IsSerializing, ///< Serializes pipeline: won't until all
+ /// older instructions have committed.
+ IsMemBarrier, ///< Is a memory barrier
+ IsWriteBarrier, ///< Is a write barrier
NumFlags
};
bool isUncondCtrl() const { return flags[IsUncondControl]; }
bool isThreadSync() const { return flags[IsThreadSync]; }
+ bool isSerializing() const { return flags[IsSerializing]; }
+ bool isMemBarrier() const { return flags[IsMemBarrier]; }
+ bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
//@}
/// Operation class. Used to select appropriate function unit in issue.
/// Return logical index (architectural reg num) of i'th destination reg.
/// Only the entries from 0 through numDestRegs()-1 are valid.
- RegIndex destRegIdx(int i) { return _destRegIdx[i]; }
+ RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
/// Return logical index (architectural reg num) of i'th source reg.
/// Only the entries from 0 through numSrcRegs()-1 are valid.
- RegIndex srcRegIdx(int i) { return _srcRegIdx[i]; }
+ RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
/// Pointer to a statically allocated "null" instruction object.
/// Used to give eaCompInst() and memAccInst() something to return
* Invalid if not a PC-relative branch (i.e. isDirectCtrl()
* should be true).
*/
- virtual Addr branchTarget(Addr branchPC)
+ virtual Addr branchTarget(Addr branchPC) const
{
panic("StaticInst::branchTarget() called on instruction "
"that is not a PC-relative branch.");
* execute the branch in question. Invalid if not an indirect
* branch (i.e. isIndirectCtrl() should be true).
*/
- virtual Addr branchTarget(ExecContext *xc)
+ virtual Addr branchTarget(ExecContext *xc) const
{
panic("StaticInst::branchTarget() called on instruction "
"that is not an indirect branch.");
Link(const std::string &name, double rate, EtherDump *dump);
~Link() {}
- virtual std::string name() const { return objName; }
+ virtual const std::string name() const { return objName; }
bool busy() const { return (bool)packet; }
bool transmit(PacketPtr &packet);
~Event() {}
- virtual std::string name() const {
+ virtual const std::string name() const {
return csprintf("Event_%x", (uintptr_t)this);
}
: objName(n), head(NULL)
{}
- virtual std::string name() const { return objName; }
+ virtual const std::string name() const { return objName; }
// schedule the given event on this queue
void schedule(Event *ev);
class Globals : public Serializable
{
public:
- string name() const;
+ const string name() const;
void serialize(ostream& os);
void unserialize(Checkpoint *cp);
};
/// The one and only instance of the Globals class.
Globals globals;
-string
+const string
Globals::name() const
{
return "Globals";
virtual ~Serializable() {}
// manditory virtual function, so objects must provide names
- virtual std::string name() const = 0;
+ virtual const std::string name() const = 0;
virtual void serialize(std::ostream& os) {}
virtual void unserialize(Checkpoint *cp, const std::string §ion) {}
virtual ~SimObject() {}
- virtual std::string name() const { return objName; }
+ virtual const std::string name() const { return objName; }
// initialization pass of all objects. Gets invoked by SimInit()
virtual void init();
projects / gem5.git / commitdiff