i965/blorp: Sanity check all layers before actual clear

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index dc2be1e72e0f215e1baae83d8e512c3cfb5d54b7..703e5471463954bd2c5d7f9ae909d7bd3d0ea670 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -720,7 +720,6 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
       }
    }
 
-   intel_miptree_check_level_layer(irb->mt, irb->mt_level, layer);
    intel_miptree_used_for_rendering(irb->mt);
 
    /* We can't setup the blorp_surf until we've allocated the MCS above */
@@ -790,12 +789,16 @@ brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
       if (rb == NULL)
          continue;
 
+      const unsigned num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
+      for (unsigned layer = 0; layer < num_layers; layer++) {
+         intel_miptree_check_level_layer(irb->mt, irb->mt_level, layer);
+      }
+
       if (fb->MaxNumLayers > 0) {
          unsigned layer_multiplier =
             (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
              irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
             irb->mt->num_samples : 1;
-         unsigned num_layers = irb->layer_count;
          for (unsigned layer = 0; layer < num_layers; layer++) {
             if (!do_single_blorp_clear(
                     brw, fb, rb, buf, partial_clear, encode_srgb,