correct fmvfgs/fmvtgs semantics, they behave like fp load/store, not frsp

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index d31198dedede5a68461f1ceb0364d89c3a81c236..7bd0d0e82d6fbec1f9912865d0e388285f14e89a 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -251,12 +251,13 @@ operations.
 * `fmvtgs. RT, FRA`
 
 move a 32-bit float from a FPR to a GPR, just copying bits. Converts the
-64-bit float in `FRA` to a 32-bit float, then writes the 32-bit float to
-`RT`. Effectively, `fmvtgs` is a macro-fusion of `frsp fmvtg`
-and therefore has the exact same exception and flags behaviour of `frsp`
+64-bit float in `FRA` to a 32-bit float, using the same method as `stfs`,
+then writes the 32-bit float to `RT`, setting the high 32-bits to zeros.
+Effectively, `fmvtgs` is a macro-fusion of `stfs` and `lwz` and therefore
+does not behave like `frsp` and does not set any fp exception flags.
 
-Unlike `frsp` however, with RT being a GPR, Rc=1 follows
-standard *integer* behaviour, i.e. tests RT and sets CR0.
+Since RT is a GPR, Rc=1 follows standard *integer* behaviour, i.e.
+tests RT and sets CR0.
 
 # GPR to FPR moves
 
@@ -270,22 +271,11 @@ Rc=1 tests FRT and sets CR1
 `fmvfgs FRT, RA`
 
 move a 32-bit float from a GPR to a FPR, just copying bits. Converts the
-32-bit float in `RA` to a 64-bit float, then writes the 64-bit float to
-`FRT`. Effectively, `fmvfgs` is a macro-fusion of `fmvfg frsp` and
-therefore has the exact same exception and flags behaviour of `frsp`
+32-bit float in `RA` to a 64-bit float, using the same method as `lfs`,
+then writes the 64-bit float to `FRT`. Effectively, `fmvfgs` is a
+macro-fusion of `stw` and `lfs` and therefore no fp exception flags are set.
 
-Rc=1 tests FRT and sets CR1
-
-TODO: clear statement on evaluation as to whether exceptions or flags raised as part of the **FP** conversion (not the int bitcopy part, the conversion part.  the semantics should really be the same as frsp)
-
-v3.0C section 4.6.7.1 states:
-
-FPRF is set to the class and sign of the result, except for Invalid Operation Exceptions when VE=1.
-
-    Special Registers Altered:
-      FPRF FR FI
-      FX OX UX XX VXSNAN
-      CR1 (if Rc=1)
+Rc=1 tests FRT and sets CR1, following usual fp Rc=1 semantics.
 
 # Conversions