Remove Minerva dependency

diff --git a/gram/simulation/simsoc.py b/gram/simulation/simsoc.py
index 90f874a06af86671e6c9472e12b826716963e5ed..4de14b7dbb01feea3a01fa2b0c955deb307e4ae9 100644 (file)
--- a/gram/simulation/simsoc.py
+++ b/gram/simulation/simsoc.py
@@ -4,11 +4,6 @@ from nmigen import *
 from nmigen.lib.cdc import ResetSynchronizer
 from nmigen_soc import wishbone, memory
 
-from lambdasoc.cpu.minerva import MinervaCPU
-from lambdasoc.periph.intc import GenericInterruptController
-from lambdasoc.periph.serial import AsyncSerialPeripheral
-from lambdasoc.periph.sram import SRAMPeripheral
-from lambdasoc.periph.timer import TimerPeripheral
 from lambdasoc.periph import Peripheral
 from lambdasoc.soc.base import SoC