+2008-02-13 Jan Beulich <jbeulich@novell.com>
+
+ * config/tc-i386.c (parse_real_register): Don't return 'FLAT'
+ if not in Intel mode.
+ (i386_intel_operand): Ignore segment overrides in immediate and
+ offset operands.
+ (intel_e11): Range-check i.mem_operands before use as array
+ index. Filter out FLAT for uses other than as segment override.
+ (intel_get_token): Remove broken promotion of "FLAT:" to mean
+ "offset FLAT:".
+
2008-02-13 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (intel_e09): Also special-case 'bound'.
&& flag_code != CODE_64BIT)
return (const reg_entry *) NULL;
+ if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
+ return (const reg_entry *) NULL;
+
return r;
}
/* Constant and OFFSET expressions are handled by i386_immediate. */
else if ((intel_parser.op_modifier & (1 << T_OFFSET))
|| intel_parser.reg == NULL)
- ret = i386_immediate (intel_parser.disp);
+ {
+ if (i.mem_operands < 2 && i.seg[i.mem_operands])
+ {
+ if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
+ as_warn (_("Segment override ignored"));
+ i.seg[i.mem_operands] = NULL;
+ }
+ ret = i386_immediate (intel_parser.disp);
+ }
if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
ret = 0;
reg->reg_name);
return 0;
}
+ else if (i.mem_operands >= 2)
+ as_warn (_("Segment override ignored"));
else if (i.seg[i.mem_operands])
as_warn (_("Extra segment override ignored"));
else
}
}
+ else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
+ {
+ as_bad (_("cannot use `FLAT' here"));
+ return 0;
+ }
+
/* Not a segment register. Check for register scaling. */
else if (cur_token.code == '*')
{
strcat (new_token.str, " FLAT:");
}
- /* ??? This is not mentioned in the MASM grammar. */
- else if (strcasecmp (new_token.str, "FLAT") == 0)
- {
- new_token.code = T_OFFSET;
- if (*q == ':')
- strcat (new_token.str, ":");
- else
- as_bad (_("`:' expected"));
- }
-
else
new_token.code = T_ID;
}
+2008-02-13 Jan Beulich <jbeulich@novell.com>
+
+ * gas/i386/intelok.s: Replace invalid offset expression with
+ valid ones.
+ * gas/i386/x86_64.s: Likewise.
+
2008-02-13 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelbad.s, gas/i386/intelok.s: Add 'bound' tests.
mov eax, offset x
mov eax, offset flat:x
- mov eax, flat:x
+ mov eax, offset gs:x
mov eax, offset [x]
mov eax, offset flat:[x]
- mov eax, flat:[x]
+ mov eax, offset gs:[x]
mov eax, [offset x]
mov eax, [eax + offset x]
mov eax, [eax + offset 1]
.intel_syntax noprefix
#immediates - various sizes:
-mov al, flat:symbol
-mov ax, flat:symbol
-mov eax, flat:symbol
-mov rax, flat:symbol
+mov al, offset flat:symbol
+mov ax, offset flat:symbol
+mov eax, offset flat:symbol
+mov rax, offset flat:symbol
#parts aren't supported by the parser, yet (and not at all for symbol refs)
#mov eax, high part symbol
+2008-02-13 Jan Beulich <jbeulich@novell.com>
+
+ * i386-opc.h (RegFlat): New.
+ * i386-reg.tbl (flat): Add.
+ * i386-tbl.h: Re-generate.
+
2008-02-13 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (a_mode): New.
/* EIZ and RIZ are fake index registers. */
#define RegEiz (RegEip - 1)
#define RegRiz (RegEiz - 1)
+/* FLAT is a fake segment register (Intel mode). */
+#define RegFlat ((unsigned char) ~0)
signed char dw2_regnum[2];
#define Dw2Inval (-1)
}
ds, SReg2, 0, 3, 43, 53
fs, SReg3, 0, 4, 44, 54
gs, SReg3, 0, 5, 45, 55
+flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval
// Control registers.
cr0, Control, 0, 0, Dw2Inval, Dw2Inval
cr1, Control, 0, 1, Dw2Inval, Dw2Inval
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0 } },
0, 5, { 45, 55 } },
+ { "flat",
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0 } },
+ 0, RegFlat, { Dw2Inval, Dw2Inval } },
{ "cr0",
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,