+Tue Jul 3 15:35:52 2001 Richard Kenner <kenner@vlsi1.ultra.nyu.edu>
+
+ * explow.c (plus_constant_wide, case PLUS): Call find_constant_term
+ and avoid checking for constant as first operand.
+ * recog.c (find_constant_term_loc): No longer static.
+ (adj_offettable_operand): Delete.
+ * rtl.h (adj_offsettable_operand): Delete declaration.
+ (find_constant_term): Add declaration.
+ * caller-save.c: Replace calls to adj_offsettable_operand with calls
+ to adjust_address.
+ * config/arm/arm.c, config/c4x/c4x.c: Likewise.
+ * config/clipper/clipper.md, config/h8300/h8300.c: Likewise.
+ * config/i386/i386.c, config/i386/i386.md: Likewise.
+ * config/i860/i860.c, config/i960/i960.c: Likewise.
+ * config/i960/i960.md, config/m68hc11/m68hc11.c: Likewise.
+ * config/m68k/m68k.c, config/m68k/m68k.md: Likewise.
+ * config/m88k/m88k.md, config/mcore/mcore.c: Likewise.
+ * config/mips/mips.c, config/mips/mips.md: Likewise.
+ * config/mn10200/mn10200.c, config/mn10300/mn10300.c: Likewise.
+ * config/ns32k/ns32k.c, config/ns32k/ns32k.md: Likewise.
+ * config/pa/pa.c, config/pdp11/pdp11.c: Likewise.
+ * config/pdp11/pdp11.md, config/sh/sh.c, config/v850/v850.c: Likewise.
+ * config/vax/vax.md, config/ns32k/ns32k.c: Likewise.
+ * config/ns32k/ns32k.md: Likewise.
+
2001-07-03 Zack Weinberg <zackw@stanford.edu>
* rtl.c (copy_rtx): Handle 'T' format letter.
/* Setup single word save area just in case... */
for (k = 0; k < j; k++)
- {
- /* This should not depend on WORDS_BIG_ENDIAN.
- The order of words in regs is the same as in memory. */
- rtx temp = gen_rtx_MEM (regno_save_mode[i + k][1],
- XEXP (regno_save_mem[i][j], 0));
-
- regno_save_mem[i + k][1]
- = adj_offsettable_operand (temp, k * UNITS_PER_WORD);
- }
+ /* This should not depend on WORDS_BIG_ENDIAN.
+ The order of words in regs is the same as in memory. */
+ regno_save_mem[i + k][1]
+ = adjust_address (regno_save_mem[i][j], regno_save_mode[i + k][1],
+ k * UNITS_PER_WORD);
}
/* Now loop again and set the alias set of any save areas we made to
}
else
{
- otherops[1] = adj_offsettable_operand (operands[1], 4);
+ otherops[1] = adjust_address (operands[1], VOIDmode, 4);
/* Take care of overlapping base/data reg. */
if (reg_mentioned_p (operands[0], operands[1]))
{
/* Fall through */
default:
- otherops[0] = adj_offsettable_operand (operands[0], 4);
+ otherops[0] = adjust_address (operands[0], VOIDmode, 4);
otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
output_asm_insn ("str%?\t%1, %0", operands);
output_asm_insn ("str%?\t%1, %0", otherops);
if (GET_CODE(op1) == CONST_INT || GET_CODE(op1) == SYMBOL_REF)
{
asm_fprintf (file, "\t%s\t@", TARGET_C3X ? "ldp" : "ldpk");
- output_address (XEXP (adj_offsettable_operand (op, 1), 0));
+ output_address (XEXP (adjust_address (op, VOIDmodem, 1), 0));
asm_fprintf (file, "\n");
}
}
if (code == MEM && c4x_autoinc_operand (op, Pmode))
break;
else if (code == MEM)
- output_address (XEXP (adj_offsettable_operand (op, 1), 0));
+ output_address (XEXP (adjust_address (op, 1), VOIDmode, 0));
else if (code == REG)
fprintf (file, "%s", reg_names[REGNO (op) + 1]);
else
;;- Machine description for GNU compiler, Clipper Version
-;; Copyright (C) 1987, 88, 91, 93, 94, 97, 98, 1999
+;; Copyright (C) 1987, 1988, 1991, 1993, 1994, 1997, 1998, 1999, 2001
;; Free Software Foundation, Inc.
;; Contributed by Holger Teutsch (holger@hotbso.rhein-main.de)
xops[0] = operands[0];
xops[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
xops[2] = operands[1];
- xops[3] = adj_offsettable_operand (operands[1], 4);
+ xops[3] = adjust_address (operands[1], SImode, 4);
output_asm_insn (\"loadw %2,%0\;loadw %3,%1\", xops);
return \"\";
}
return \"stord %1,%0\";
xops[0] = operands[0]; /* r -> o */
- xops[1] = adj_offsettable_operand (operands[0], 4);
+ xops[1] = adjust_address (operands[0], SImode, 4);
xops[2] = operands[1];
xops[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops);
}
/* m -> r */
output_asm_insn (\"loadw %1,%0\", operands);
- xoperands[1] = adj_offsettable_operand (operands[1], 4);
+ xoperands[1] = adjust_address (operands[1], SImode, 4);
output_asm_insn (\"loadw %1,%0\", xoperands);
return \"\";
}"
{
rtx xops[4];
xops[0] = operands[0];
- xops[1] = adj_offsettable_operand (operands[0], 4);
+ xops[1] = adjust_address (operands[0], SImode, 4);
xops[2] = operands[1];
xops[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops);
fprintf (file, "%s", names_upper_extended[REGNO (x)]);
break;
case MEM:
- x = adj_offsettable_operand (x, 0);
print_operand (file, x, 0);
break;
case CONST_INT:
fprintf (file, "%s", names_big[REGNO (x)]);
break;
case MEM:
- x = adj_offsettable_operand (x, 2);
+ x = adjust_address (x, HImode, 2);
print_operand (file, x, 0);
break;
case CONST_INT:
is restored from POINTER + OFFSET. */
static void
ix86_emit_save_regs_using_mov (pointer, offset)
- rtx pointer;
- HOST_WIDE_INT offset;
+ rtx pointer;
+ HOST_WIDE_INT offset;
{
int regno;
rtx insn;
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
if (ix86_save_reg (regno, true))
{
- insn = emit_move_insn (adj_offsettable_operand (gen_rtx_MEM (Pmode,
- pointer),
- offset),
+ insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
+ Pmode, offset),
gen_rtx_REG (Pmode, regno));
RTX_FRAME_RELATED_P (insn) = 1;
offset += UNITS_PER_WORD;
if (ix86_save_reg (regno, maybe_eh_return))
{
emit_move_insn (gen_rtx_REG (Pmode, regno),
- adj_offsettable_operand (gen_rtx_MEM (Pmode,
- pointer),
- offset));
+ adjust_address (gen_rtx_MEM (Pmode, pointer),
+ Pmode, offset));
offset += UNITS_PER_WORD;
}
}
}
else if (offsettable_memref_p (op))
{
- rtx hi_addr = XEXP (adj_offsettable_operand (op, 4), 0);
-
lo_half[num] = adjust_address (op, SImode, 0);
- hi_half[num] = change_address (op, SImode, hi_addr);
+ hi_half[num] = adjust_address (op, SImode, 4);
}
else
abort ();
{
operand = adjust_address (operand, SImode, 0);
parts[0] = operand;
- parts[1] = adj_offsettable_operand (operand, 4);
+ parts[1] = adjust_address (operand, SImode, 4);
if (size == 3)
- parts[2] = adj_offsettable_operand (operand, 8);
+ parts[2] = adjust_address (operand, SImode, 8);
}
else if (GET_CODE (operand) == CONST_DOUBLE)
{
}
else if (offsettable_memref_p (operand))
{
- operand = change_address (operand, DImode, XEXP (operand, 0));
+ operand = adjust_address (operand, DImode, 0);
parts[0] = operand;
- parts[1] = adj_offsettable_operand (operand, 8);
- parts[1] = change_address (parts[1], SImode, XEXP (parts[1], 0));
+ parts[1] = adjust_address (operand, SImode, 8);
}
else if (GET_CODE (operand) == CONST_DOUBLE)
{
part[1][0] = change_address (part[1][0],
TARGET_64BIT ? DImode : SImode,
part[0][nparts - 1]);
- part[1][1] = adj_offsettable_operand (part[1][0],
- UNITS_PER_WORD);
- part[1][1] = change_address (part[1][1], GET_MODE (part[0][1]),
- XEXP (part[1][1], 0));
+ part[1][1] = adjust_address (part[1][0], VOIDmode, UNITS_PER_WORD);
if (nparts == 3)
- part[1][2] = adj_offsettable_operand (part[1][0], 8);
+ part[1][2] = adjust_address (part[1][0], VOIDmode, 8);
}
}
case IX86_BUILTIN_SETPS:
target = assign_386_stack_local (V4SFmode, 0);
- op0 = adjust_address (target, SFmode, 0);
arg0 = TREE_VALUE (arglist);
arg1 = TREE_VALUE (TREE_CHAIN (arglist));
arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
- emit_move_insn (op0,
+ emit_move_insn (adjust_address (op0, SFmode, 0),
expand_expr (arg0, NULL_RTX, VOIDmode, 0));
- emit_move_insn (adj_offsettable_operand (op0, 4),
+ emit_move_insn (adjust_address (op0, SFmode, 4),
expand_expr (arg1, NULL_RTX, VOIDmode, 0));
- emit_move_insn (adj_offsettable_operand (op0, 8),
+ emit_move_insn (adjust_address (op0, SFmode, 8),
expand_expr (arg2, NULL_RTX, VOIDmode, 0));
- emit_move_insn (adj_offsettable_operand (op0, 12),
+ emit_move_insn (adjust_address (op0, SFmode, 12),
expand_expr (arg3, NULL_RTX, VOIDmode, 0));
op0 = gen_reg_rtx (V4SFmode);
emit_insn (gen_sse_movaps (op0, target));
/* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
if (size >= 12)
size = 10;
- operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
- operands[0] = adj_offsettable_operand (operands[0], size - 1);
+ operands[0] = adjust_address (operands[0], QImode, size - 1);
operands[1] = GEN_INT (trunc_int_for_mode (0x80, QImode));
})
/* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
if (size >= 12)
size = 10;
- operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
- operands[0] = adj_offsettable_operand (operands[0], size - 1);
+ operands[0] = adjust_address (operands[0], QImode, size - 1);
operands[1] = GEN_INT (trunc_int_for_mode (~0x80, QImode));
})
/* Subroutines for insn-output.c for Intel 860
- Copyright (C) 1989, 1991, 1997, 1998, 1999, 2000
+ Copyright (C) 1989, 1991, 1997, 1998, 1999, 2000, 2001
Free Software Foundation, Inc.
Derived from sparc.c.
if (optype0 == REGOP)
latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else if (optype0 == OFFSOP)
- latehalf[0] = adj_offsettable_operand (operands[0], 4);
+ latehalf[0] = adjust_address (operands[0], SImode, 4);
else
latehalf[0] = operands[0];
if (optype1 == REGOP)
latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else if (optype1 == OFFSOP)
- latehalf[1] = adj_offsettable_operand (operands[1], 4);
+ latehalf[1] = adjust_address (operands[1], SImode, 4);
else if (optype1 == CNSTOP)
{
if (GET_CODE (operands[1]) == CONST_DOUBLE)
xops[1] = operands[0];
output_asm_insn ("adds %1,%0,%1", xops);
operands[1] = gen_rtx_MEM (DImode, operands[0]);
- latehalf[1] = adj_offsettable_operand (operands[1], 4);
+ latehalf[1] = adjust_address (operands[1], SImode, 4);
addreg1 = 0;
highest_first = 1;
}
/* Subroutines used for code generation on intel 80960.
- Copyright (C) 1992, 1995, 1996, 1997, 1998, 1999, 2000
+ Copyright (C) 1992, 1995, 1996, 1997, 1998, 1999, 2000, 2001
Free Software Foundation, Inc.
Contributed by Steven McGeady, Intel Corp.
Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
operands[1] = src;
operands[2] = gen_rtx_REG (Pmode, REGNO (dst) + 1);
operands[3] = gen_rtx_MEM (word_mode, operands[2]);
- operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
- output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands);
+ operands[4] = adjust_address (operands[3], word_mode,
+ UNITS_PER_WORD);
+ output_asm_insn
+ ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands);
return "";
}
else
if (REGNO (src) & 1)
{
operands[0] = dst;
- operands[1] = adj_offsettable_operand (dst, UNITS_PER_WORD);
+ operands[1] = adjust_address (dst, word_mode, UNITS_PER_WORD);
if (! memory_address_p (word_mode, XEXP (operands[1], 0)))
abort ();
operands[2] = src;
operands[0] = dst;
{
- operands[1] = adj_offsettable_operand (dst, 4);
+ operands[1] = adjust_address (dst, word_mode, 4);
output_asm_insn ("st g14,%0\n\tst g14,%1", operands);
}
return "";
operands[1] = src;
operands[2] = gen_rtx_REG (Pmode, REGNO (dst) + 3);
operands[3] = gen_rtx_MEM (word_mode, operands[2]);
- operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
- operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD);
- operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD);
+ operands[4]
+ = adjust_address (operands[3], word_mode, UNITS_PER_WORD);
+ operands[5]
+ = adjust_address (operands[4], word_mode, UNITS_PER_WORD);
+ operands[6]
+ = adjust_address (operands[5], word_mode, UNITS_PER_WORD);
output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands);
return "";
}
if (REGNO (src) & 3)
{
operands[0] = dst;
- operands[1] = adj_offsettable_operand (dst, UNITS_PER_WORD);
- operands[2] = adj_offsettable_operand (dst, 2*UNITS_PER_WORD);
- operands[3] = adj_offsettable_operand (dst, 3*UNITS_PER_WORD);
+ operands[1] = adjust_address (dst, word_mode, UNITS_PER_WORD);
+ operands[2] = adjust_address (dst, word_mode, 2 * UNITS_PER_WORD);
+ operands[3] = adjust_address (dst, word_mode, 3 * UNITS_PER_WORD);
if (! memory_address_p (word_mode, XEXP (operands[3], 0)))
abort ();
operands[4] = src;
operands[0] = dst;
{
- operands[1] = adj_offsettable_operand (dst, 4);
- operands[2] = adj_offsettable_operand (dst, 8);
- operands[3] = adj_offsettable_operand (dst, 12);
+ operands[1] = adjust_address (dst, word_mode, 4);
+ operands[2] = adjust_address (dst, word_mode, 8);
+ operands[3] = adjust_address (dst, word_mode, 12);
output_asm_insn ("st g14,%0\n\tst g14,%1\n\tst g14,%2\n\tst g14,%3", operands);
}
return "";
;;- Machine description for Intel 80960 chip for GNU C compiler
-;; Copyright (C) 1992, 1995, 1998 Free Software Foundation, Inc.
+;; Copyright (C) 1992, 1995, 1998, 2001 Free Software Foundation, Inc.
;; Contributed by Steven McGeady, Intel Corp.
;; Additional work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
;; Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
return i960_output_move_double (operands[0], operands[1]);
operands[3] = gen_rtx_MEM (word_mode, operands[2]);
- operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
+ operands[4] = adjust_address (operands[3], word_mode, UNITS_PER_WORD);
return \"lda %0,%2\;st %1,%3\;st %D1,%4\";
}"
[(set_attr "type" "move,store")])
return i960_output_move_quad (operands[0], operands[1]);
operands[3] = gen_rtx_MEM (word_mode, operands[2]);
- operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
- operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD);
- operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD);
+ operands[4] = adjust_address (operands[3], word_mode, UNITS_PER_WORD);
+ operands[5] = adjust_address (operands[4], word_mode, UNITS_PER_WORD);
+ operands[6] = adjust_address (operands[5], word_mode, UNITS_PER_WORD);
return \"lda %0,%2\;st %1,%3\;st %D1,%4\;st %E1,%5\;st %F1,%6\";
}"
[(set_attr "type" "move,store")])
case 4:
return \"stl %1,%0\";
case 5:
- operands[1] = adj_offsettable_operand (operands[0], 4);
+ operands[1] = adjust_address (operands[0], VOIDmode, 4);
return \"st g14,%0\;st g14,%1\";
}
}"
if (offset)
{
- high_from = adj_offsettable_operand (high_from, offset);
+ high_from = adjust_address (high_from, mode, offset);
low_from = high_from;
}
if (mode == SImode)
if (GET_CODE (operand1) == REG)
loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
else
- loperands[1] = adj_offsettable_operand (operand1, 4);
+ loperands[1] = adjust_address (operand1, SImode, 4);
if (operand2 != const0_rtx)
{
loperands[2] = operand2;
if (GET_CODE (operand2) == REG)
loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
else
- loperands[3] = adj_offsettable_operand (operand2, 4);
+ loperands[3] = adjust_address (operand2, SImode, 4);
}
loperands[4] = gen_label_rtx();
if (operand2 != const0_rtx)
{
int offset = (count & ~signpos) / 8;
count = count & signpos;
- operands[1] = dataop = adj_offsettable_operand (dataop, offset);
+ operands[1] = dataop = adjust_address (dataop, QImode, offset);
}
if (count == signpos)
cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
}
else if (optype0 == OFFSOP)
{
- middlehalf[0] = adj_offsettable_operand (operands[0], 4);
- latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
+ middlehalf[0] = adjust_address (operands[0], SImode, 4);
+ latehalf[0] = adjust_address (operands[0], SImode, size - 4);
}
else
{
}
else if (optype1 == OFFSOP)
{
- middlehalf[1] = adj_offsettable_operand (operands[1], 4);
- latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
+ middlehalf[1] = adjust_address (operands[1], SImode, 4);
+ latehalf[1] = adjust_address (operands[1], SImode, size - 4);
}
else if (optype1 == CNSTOP)
{
if (optype0 == REGOP)
latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else if (optype0 == OFFSOP)
- latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
+ latehalf[0] = adjust_address (operands[0], SImode, size - 4);
else
latehalf[0] = operands[0];
if (optype1 == REGOP)
latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else if (optype1 == OFFSOP)
- latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
+ latehalf[1] = adjust_address (operands[1], SImode, size - 4);
else if (optype1 == CNSTOP)
split_double (operands[1], &operands[1], &latehalf[1]);
else
xops[0] = latehalf[0];
xops[1] = XEXP (operands[1], 0);
output_asm_insn ("lea %a1,%0", xops);
- if( GET_MODE (operands[1]) == XFmode )
+ if (GET_MODE (operands[1]) == XFmode )
{
operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
- middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
- latehalf[1] = adj_offsettable_operand (operands[1], size-4);
+ middlehalf[1] = adjust_address (operands[1], DImode, size - 8);
+ latehalf[1] = adjust_address (operands[1], DImode, size - 4);
}
else
{
operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
- latehalf[1] = adj_offsettable_operand (operands[1], size-4);
+ latehalf[1] = adjust_address (operands[1], DImode, size - 4);
}
}
else if (size == 12
&& !TARGET_5200)
{
if (GET_CODE (operands[0]) != REG)
- operands[0] = adj_offsettable_operand (operands[0], 2);
+ operands[0] = adjust_address (operands[0], HImode, 2);
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
/* Do not delete a following tstl %0 insn; that would be incorrect. */
CC_STATUS_INIT;
}
else
{
- operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
+ operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
operands[1] = GEN_INT (logval % 8);
}
/* This does not set condition codes in a standard way. */
&& !TARGET_5200)
{
if (GET_CODE (operands[0]) != REG)
- operands[0] = adj_offsettable_operand (operands[0], 2);
+ operands[0] = adjust_address (operands[0], HImode, 2);
/* Do not delete a following tstl %0 insn; that would be incorrect. */
CC_STATUS_INIT;
if (INTVAL (operands[2]) == 0xffff)
|| offsettable_memref_p (operands[0])))
{
if (DATA_REG_P (operands[0]))
- {
- operands[1] = GEN_INT (logval);
- }
+ operands[1] = GEN_INT (logval);
else
{
- operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
+ operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
operands[1] = GEN_INT (logval % 8);
}
CC_STATUS_INIT;
&& !TARGET_5200)
{
if (! DATA_REG_P (operands[0]))
- operands[0] = adj_offsettable_operand (operands[0], 2);
+ operands[0] = adjust_address (operands[0], HImode, 2);
/* Do not delete a following tstl %0 insn; that would be incorrect. */
CC_STATUS_INIT;
if (INTVAL (operands[2]) == 0xffff)
|| offsettable_memref_p (operands[0])))
{
if (DATA_REG_P (operands[0]))
- {
- operands[1] = GEN_INT (logval);
- }
+ operands[1] = GEN_INT (logval);
else
{
- operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
+ operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
operands[1] = GEN_INT (logval % 8);
}
CC_STATUS_INIT;
{
if (GET_CODE (operands[0]) == MEM)
{
- operands[0] = adj_offsettable_operand (operands[0],
- INTVAL (operands[1]) / 8);
+ operands[0] = adjust_address (operands[0], QImode,
+ INTVAL (operands[1]) / 8);
operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
return output_btst (operands, operands[1], operands[0], insn, 7);
}
{
if (GET_CODE (operands[0]) == MEM)
{
- operands[0] = adj_offsettable_operand (operands[0],
- INTVAL (operands[1]) / 8);
+ operands[0] = adjust_address (operands[0], QImode,
+ INTVAL (operands[1]) / 8);
operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
return output_btst (operands, operands[1], operands[0], insn, 7);
}
return \"move%.l %1,%0\";
}
if (GET_CODE (operands[1]) == MEM)
- operands[1] = adj_offsettable_operand (operands[1], 3);
+ operands[1] = adjust_address (operands[1], QImode, 3);
return \"move%.b %1,%0\";
}")
return \"move%.l %1,%0\";
}
if (GET_CODE (operands[1]) == MEM)
- operands[1] = adj_offsettable_operand (operands[1], 1);
+ operands[1] = adjust_address (operands[1], QImode, 1);
return \"move%.b %1,%0\";
}")
return \"move%.l %1,%0\";
}
if (GET_CODE (operands[1]) == MEM)
- operands[1] = adj_offsettable_operand (operands[1], 2);
+ operands[1] = adjust_address (operands[1], QImode, 2);
return \"move%.w %1,%0\";
}")
\f
else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
return \"clr%.l %0\;move%.l %1,%0\";
else
- operands[2] = adj_offsettable_operand (operands[0], 4);
+ operands[2] = adjust_address (operands[0], SImode, 4);
if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
|| REGNO (operands[1]) != REGNO (operands[2]))
output_asm_insn (\"move%.l %1,%2\", operands);
else
{
output_asm_insn (\"clr%.w %0\", operands);
- operands[0] = adj_offsettable_operand (operands[0], 2);
+ operands[0] = adjust_address (operands[0], HImode, 2);
return \"move%.w %1,%0\";
}
}")
else
{
output_asm_insn (\"clr%.b %0\", operands);
- operands[0] = adj_offsettable_operand (operands[0], 1);
+ operands[0] = adjust_address (operands[0], QImode, 1);
return \"move%.b %1,%0\";
}
}")
else
{
output_asm_insn (\"clr%.l %0\", operands);
- operands[0] = adj_offsettable_operand (operands[0], 3);
+ operands[0] = adjust_address (operands[0], QImode, 3);
return \"move%.b %1,%0\";
}
}")
|| GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
operands[4] = operands[1];
else
- operands[4] = adj_offsettable_operand (operands[1], 4);
+ operands[4] = adjust_address (operands[1], SImode, 4);
if (GET_CODE (operands[1]) == MEM
&& GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
output_asm_insn (\"move%.l %4,%3\", operands);
if (GET_CODE (operands[0]) == REG)
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
- operands[2] = adj_offsettable_operand (operands[0], 4);
+ operands[2] = adjust_address (operands[0], SImode, 4);
return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
} ")
if (GET_CODE (operands[1]) == REG)
operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
- operands[1] = adj_offsettable_operand (operands[1], 4);
+ operands[1] = adjust_address (operands[1], SImode, 4);
return \"add%.l %1,%0\";
} ")
split_double (operands[2], &high, &low);
else
{
- low = adj_offsettable_operand (operands[2], 4);
+ low = adjust_address (operands[2], SImode, 4);
high = operands[2];
}
}
else
{
- operands[1] = adj_offsettable_operand (operands[0], 4);
+ operands[1] = adjust_address (operands[0], SImode, 4);
return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
}
}
if (GET_CODE (operands[1]) == REG)
operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
- operands[1] = adj_offsettable_operand (operands[1], 4);
+ operands[1] = adjust_address (operands[1], SImode, 4);
return \"sub%.l %1,%0\";
} ")
split_double (operands[2], &high, &low);
else
{
- low = adj_offsettable_operand (operands[2], 4);
+ low = adjust_address (operands[2], SImode, 4);
high = operands[2];
}
}
else
{
- operands[1] = adj_offsettable_operand (operands[0], 4);
+ operands[1] = adjust_address (operands[0], SImode, 4);
return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
}
}
if (GET_CODE (operands[0]) == REG)
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
- operands[0] = adj_offsettable_operand (operands[0], 4);
+ operands[0] = adjust_address (operands[0], SImode, 4);
switch (INTVAL (lo))
{
case 0 :
}
if (GET_CODE (operands[0]) != REG)
{
- operands[1] = adj_offsettable_operand (operands[0], 4);
+ operands[1] = adjust_address (operands[0], SImode, 4);
return \"and%.l %2,%0\;and%.l %R2,%1\";
}
if (GET_CODE (operands[2]) != REG)
{
- operands[1] = adj_offsettable_operand (operands[2], 4);
+ operands[1] = adjust_address (operands[2], SImode, 4);
return \"and%.l %2,%0\;and%.l %1,%R0\";
}
return \"and%.l %2,%0\;and%.l %R2,%R0\";
if (GET_CODE (operands[0]) == REG)
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
- operands[0] = adj_offsettable_operand (operands[0], 4);
+ operands[0] = adjust_address (operands[0], SImode, 4);
if (GET_MODE (operands[1]) == SImode)
return \"or%.l %1,%0\";
byte_mode = (GET_MODE (operands[1]) == QImode);
if (GET_CODE (operands[0]) == MEM)
- operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
+ operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
+ byte_mode ? 3 : 2);
if (byte_mode)
return \"or%.b %1,%0\";
else
if (GET_CODE (operands[0]) == REG)
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
- operands[0] = adj_offsettable_operand (operands[0], 4);
+ operands[0] = adjust_address (operands[0], SImode, 4);
switch (INTVAL (lo))
{
case 0 :
}
if (GET_CODE (operands[0]) != REG)
{
- operands[1] = adj_offsettable_operand (operands[0], 4);
+ operands[1] = adjust_address (operands[0], SImode, 4);
return \"or%.l %2,%0\;or%.l %R2,%1\";
}
if (GET_CODE (operands[2]) != REG)
{
- operands[1] = adj_offsettable_operand (operands[2], 4);
+ operands[1] = adjust_address (operands[2], SImode, 4);
return \"or%.l %2,%0\;or%.l %1,%R0\";
}
return \"or%.l %2,%0\;or%.l %R2,%R0\";
{
CC_STATUS_INIT;
if (GET_CODE (operands[2]) != REG)
- operands[2] = adj_offsettable_operand (operands[2], 2);
+ operands[2] = adjust_address (operands[2], HImode, 2);
if (GET_CODE (operands[2]) != REG
|| REGNO (operands[2]) != REGNO (operands[0]))
output_asm_insn (\"move%.w %2,%0\", operands);
CC_STATUS_INIT;
byte_mode = (GET_MODE (operands[1]) == QImode);
if (GET_CODE (operands[0]) == MEM)
- operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
+ operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
+ byte_mode ? 3 : 2);
if (byte_mode)
return \"or%.b %1,%0\";
else
if (GET_CODE (operands[0]) == REG)
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
- operands[0] = adj_offsettable_operand (operands[0], 4);
+ operands[0] = adjust_address (operands[0], SImode, 4);
switch (INTVAL (lo))
{
case 0 :
}
if (GET_CODE (operands[0]) != REG)
{
- operands[1] = adj_offsettable_operand (operands[0], 4);
+ operands[1] = adjust_address (operands[0], SImode, 4);
return \"eor%.l %2,%0\;eor%.l %R2,%1\";
}
if (GET_CODE (operands[2]) != REG)
{
- operands[1] = adj_offsettable_operand (operands[2], 4);
+ operands[1] = adjust_address (operands[2], SImode, 4);
return \"eor%.l %2,%0\;eor%.l %1,%R0\";
}
return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
if (GET_CODE (operands[0]) == REG)
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
- operands[1] = adj_offsettable_operand (operands[0], 4);
+ operands[1] = adjust_address (operands[0], SImode, 4);
if (ADDRESS_REG_P (operands[0]))
return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
else
|| GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
operands[1] = operands[0];
else
- operands[1] = adj_offsettable_operand (operands[0], 4);
+ operands[1] = adjust_address (operands[0], SImode, 4);
return \"not%.l %1\;not%.l %0\";
}")
if (GET_CODE (operands[0]) == REG)
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
- operands[2] = adj_offsettable_operand (operands[0], 4);
+ operands[2] = adjust_address (operands[0], SImode, 4);
if (ADDRESS_REG_P (operands[0]))
return \"move%.l %1,%0\;sub%.l %2,%2\";
else
return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
else
{
- operands[3] = adj_offsettable_operand (operands[0], 4);
+ operands[3] = adjust_address (operands[0], SImode, 4);
return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
}
}
if (GET_CODE (operands[1]) == REG)
operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
- operands[3] = adj_offsettable_operand (operands[1], 4);
+ operands[3] = adjust_address (operands[1], SImode, 4);
if (GET_CODE (operands[0]) == REG)
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
return \"move%.l %3,%0\;clr%.l %0\";
else
- operands[2] = adj_offsettable_operand (operands[0], 4);
+ operands[2] = adjust_address (operands[0], SImode, 4);
if (ADDRESS_REG_P (operands[2]))
return \"move%.l %3,%0\;sub%.l %2,%2\";
else
"*
{
if (GET_CODE (operands[1]) != REG)
- operands[1] = adj_offsettable_operand (operands[1], 2);
+ operands[1] = adjust_address (operands[1], HImode, 2);
return \"move%.w %1,%0\";
} ")
if (which_alternative == 1)
operands[3] = operands[0];
else
- operands[3] = adj_offsettable_operand (operands[0], 4);
+ operands[3] = adjust_address (operands[0], SImode, 4);
if (TARGET_68020)
return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
else
;; if (GET_CODE (operands[1]) == REG)
;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
;; else
-;; operands[2] = adj_offsettable_operand (operands[1], 4);
+;; operands[2] = adjust_address (operands[1], SImode, 4);
;; return \"move%.l %0,%2\;clr%.l %1\";
;;} ")
if (GET_CODE (operands[0]) == REG)
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
- operands[2] = adj_offsettable_operand (operands[0], 4);
+ operands[2] = adjust_address (operands[0], SImode, 4);
if (GET_CODE (operands[1]) == REG)
operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
- operands[3] = adj_offsettable_operand (operands[1], 4);
+ operands[3] = adjust_address (operands[1], SImode, 4);
if (ADDRESS_REG_P (operands[0]))
return \"move%.l %1,%2\;sub%.l %0,%0\";
else
"*
{
operands[0]
- = adj_offsettable_operand (operands[0], INTVAL (operands[1]) / 8);
+ = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
return \"move%.l %2,%0\";
}")
return \"bfins %3,%0{%b2:%b1}\";
}
else
- operands[0]
- = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
+ operands[0] = adjust_address (operands[0],
+ INTVAL (operands[1]) == 8 ? QImode : HImode,
+ INTVAL (operands[2]) / 8);
if (GET_CODE (operands[3]) == MEM)
- operands[3] = adj_offsettable_operand (operands[3],
- (32 - INTVAL (operands[1])) / 8);
+ operands[3] = adjust_address (operands[3],
+ INTVAL (operands[1]) == 8 ? QImode : HImode,
+ (32 - INTVAL (operands[1])) / 8);
+
if (INTVAL (operands[1]) == 8)
return \"move%.b %3,%0\";
return \"move%.w %3,%0\";
"*
{
operands[1]
- = adj_offsettable_operand (operands[1], INTVAL (operands[2]) / 8);
+ = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
return \"move%.l %1,%0\";
}")
}
else
operands[1]
- = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
+ = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
output_asm_insn (\"clr%.l %0\", operands);
if (GET_CODE (operands[0]) == MEM)
- operands[0] = adj_offsettable_operand (operands[0],
- (32 - INTVAL (operands[1])) / 8);
+ operands[0] = adjust_address (operands[0],
+ INTVAL (operands[2]) == 8 ? QImode : HImode,
+ (32 - INTVAL (operands[1])) / 8);
+
if (INTVAL (operands[2]) == 8)
return \"move%.b %1,%0\";
return \"move%.w %1,%0\";
"*
{
operands[1]
- = adj_offsettable_operand (operands[1], INTVAL (operands[2]) / 8);
+ = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
return \"move%.l %1,%0\";
}")
}
else
operands[1]
- = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
+ = adjust_address (operands[1],
+ INTVAL (operands[2]) == 8 ? QImode : HImode,
+ INTVAL (operands[3]) / 8);
if (INTVAL (operands[2]) == 8)
return \"move%.b %1,%0\;extb%.l %0\";
if (GET_CODE (operands[0]) == REG)
operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
- operands[3] = adj_offsettable_operand (operands[0], 4);
+ operands[3] = adjust_address (operands[0], SImode, 4);
if (! ADDRESS_REG_P (operands[0]))
{
if (reg_overlap_mentioned_p (operands[2], operands[0]))
if (GET_CODE (operands[0]) == REG)
operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
- operands[3] = adj_offsettable_operand (operands[0], 4);
+ operands[3] = adjust_address (operands[0], SImode, 4);
if (!ADDRESS_REG_P (operands[0]))
{
if (reg_overlap_mentioned_p (operands[2], operands[0]))
; case 0:
; return \"or %0,%#r0,0\;or %d0,%#r0,0\";
; case 1:
-; operands[1] = adj_offsettable_operand (operands[0], 4);
+; operands[1] = adjust_address (operands[0], SImode, 4);
; return \"%v0st\\t %#r0,%0\;st %#r0,%1\";
; }
;}")
fputs (reg_names[REGNO (x) + 1], (stream));
break;
case MEM:
- mcore_print_operand_address (stream,
- XEXP (adj_offsettable_operand (x, 4), 0));
+ mcore_print_operand_address
+ (stream, XEXP (adjust_address (x, SImode, 4), 0));
break;
default:
abort ();
else if (double_memory_operand (op1, GET_MODE (op1)))
{
- operands[2] = adj_offsettable_operand (op1, 4);
+ operands[2] = adjust_address (op1, SImode, 4);
ret = (reg_mentioned_p (op0, op1)
? "lw\t%D0,%2\n\tlw\t%0,%1"
: "lw\t%0,%1\n\tlw\t%D0,%2");
else if (double_memory_operand (op0, GET_MODE (op0)))
{
- operands[2] = adj_offsettable_operand (op0, 4);
+ operands[2] = adjust_address (op0, SImode, 4);
ret = "sw\t%1,%0\n\tsw\t%D1,%2";
}
}
ret = "sd\t%.,%0";
else
{
- operands[2] = adj_offsettable_operand (op0, 4);
+ operands[2] = adjust_address (op0, SImode, 4);
ret = "sw\t%.,%0\n\tsw\t%.,%2";
}
}
scratch = gen_rtx_REG (SImode, REGNO (scratch));
memword = adjust_address (op1, SImode, 0);
- offword = change_address (adj_offsettable_operand (op1, 4),
- SImode, NULL_RTX);
+ offword = adjust_address (op1, SImode, 4);
+
if (BYTES_BIG_ENDIAN)
{
hi_word = memword;
scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
memword = adjust_address (op0, SImode, 0);
- offword = change_address (adj_offsettable_operand (op0, 4),
- SImode, NULL_RTX);
+ offword = adjust_address (op0, SImode, 4);
+
if (BYTES_BIG_ENDIAN)
{
hi_word = memword;
/* Subroutines for insn-output.c for Matsushita MN10200 series
- Copyright (C) 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+ Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Contributed by Jeff Law (law@cygnus.com).
This file is part of GNU CC.
{
case MEM:
fputc ('(', file);
- x = adj_offsettable_operand (x, 2);
+ x = adjust_address (x, HImode, 2);
output_address (XEXP (x, 0));
fputc (')', file);
break;
{
case MEM:
fputc ('(', file);
- x = adj_offsettable_operand (x, 4);
+ x = adjust_address (x, SImode, 4);
output_address (XEXP (x, 0));
fputc (')', file);
break;
else if (offsettable_memref_p (operands[num]))
{
lo_half[num] = operands[num];
- hi_half[num] = adj_offsettable_operand (operands[num], 4);
+ hi_half[num] = adjust_address (operands[num], SImode, 4);
}
else
abort ();
if (optype0 == REGOP)
latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else if (optype0 == OFFSOP)
- latehalf[0] = adj_offsettable_operand (operands[0], 4);
+ latehalf[0] = adjust_address (operands[0], SImode, 4);
else
latehalf[0] = operands[0];
if (optype1 == REGOP)
latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else if (optype1 == OFFSOP)
- latehalf[1] = adj_offsettable_operand (operands[1], 4);
+ latehalf[1] = adjust_address (operands[1], SImode, 4);
else if (optype1 == CNSTOP)
split_double (operands[1], &operands[1], &latehalf[1]);
else
xops[1] = operands[0];
output_asm_insn ("addr %a0,%1", xops);
operands[1] = gen_rtx_MEM (DImode, operands[0]);
- latehalf[1] = adj_offsettable_operand (operands[1], 4);
+ latehalf[1] = adjust_address (operands[1], SImode, 4);
/* The first half has the overlap, Do the late half first. */
output_asm_insn (singlemove_string (latehalf), latehalf);
/* Then clobber. */
;;- Machine description for GNU compiler, ns32000 Version
-;; Copyright (C) 1988, 1994, 1996, 1998, 1999, 2000
+;; Copyright (C) 1988, 1994, 1996, 1998, 1999, 2000, 2001
;; Free Software Foundation, Inc.
;; Contributed by Michael Tiemann (tiemann@cygnus.com)
{
if (INTVAL (operands[2]) >= 8)
{
- operands[0] = adj_offsettable_operand (operands[0],
- INTVAL (operands[2]) / 8);
+ operands[0] = adjust_address (operands[0], QImode,
+ INTVAL (operands[2]) / 8);
operands[2] = GEN_INT (INTVAL (operands[2]) % 8);
}
if (INTVAL (operands[1]) <= 8)
if (optype0 == REGOP)
latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else if (optype0 == OFFSOP)
- latehalf[0] = adj_offsettable_operand (operands[0], 4);
+ latehalf[0] = adjust_address (operands[0], SImode, 4);
else
latehalf[0] = operands[0];
if (optype1 == REGOP)
latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else if (optype1 == OFFSOP)
- latehalf[1] = adj_offsettable_operand (operands[1], 4);
+ latehalf[1] = adjust_address (operands[1], SImode, 4);
else if (optype1 == CNSTOP)
split_double (operands[1], &operands[1], &latehalf[1]);
else
/* Subroutines for gcc2 for pdp11.
- Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999
+ Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2001
Free Software Foundation, Inc.
Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
if (optype0 == REGOP)
latehalf[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
else if (optype0 == OFFSOP)
- latehalf[0] = adj_offsettable_operand (operands[0], 2);
+ latehalf[0] = adjust_address (operands[0], HImode, 2);
else
latehalf[0] = operands[0];
if (optype1 == REGOP)
latehalf[1] = gen_rtx_REG (HImode, REGNO (operands[1]) + 1);
else if (optype1 == OFFSOP)
- latehalf[1] = adj_offsettable_operand (operands[1], 2);
+ latehalf[1] = adjust_address (operands[1], HImode, 2);
else if (optype1 == CNSTOP)
{
if (CONSTANT_P (operands[1]))
if (optype0 == REGOP)
latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
else if (optype0 == OFFSOP)
- latehalf[0] = adj_offsettable_operand (operands[0], 4);
+ latehalf[0] = adjust_address (operands[0], SImode, 4);
else
latehalf[0] = operands[0];
if (optype1 == REGOP)
latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
else if (optype1 == OFFSOP)
- latehalf[1] = adj_offsettable_operand (operands[1], 4);
+ latehalf[1] = adjust_address (operands[1], SImode, 4);
else if (optype1 == CNSTOP)
{
if (GET_CODE (operands[1]) == CONST_DOUBLE)
;;- Machine description for the pdp11 for GNU C compiler
-;; Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000
+;; Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001
;; Free Software Foundation, Inc.
;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
/* we don't want to mess with auto increment */
- switch(which_alternative)
+ switch (which_alternative)
{
case 0:
latehalf[0] = operands[0];
- operands[0] = adj_offsettable_operand(operands[0], 2);
+ operands[0] = adjust_address(operands[0], HImode, 2);
output_asm_insn(\"mov %1, %0\", operands);
output_asm_insn(\"sxt %0\", latehalf);
if (REG_P (operands[0]))
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
else
- operands[0] = adj_offsettable_operand (operands[0], 2);
+ operands[0] = adjust_address (operands[0], HImode, 2);
if (! CONSTANT_P(operands[2]))
{
if (REG_P (operands[2]))
operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
else
- operands[2] = adj_offsettable_operand(operands[2], 2);
+ operands[2] = adjust_address (operands[2], HImode, 2);
output_asm_insn (\"add %2, %0\", operands);
output_asm_insn (\"adc %0\", lateoperands);
if (REG_P (operands[0]))
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
else
- operands[0] = adj_offsettable_operand (operands[0], 2);
+ operands[0] = adjust_address (operands[0], HImode, 2);
lateoperands[2] = operands[2];
if (REG_P (operands[2]))
operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
else
- operands[2] = adj_offsettable_operand(operands[2], 2);
+ operands[2] = adjust_address (operands[2], HImode, 2);
output_asm_insn (\"sub %2, %0\", operands);
output_asm_insn (\"sbc %0\", lateoperands);
if (REG_P (operands[0]))
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
else
- operands[0] = adj_offsettable_operand (operands[0], 2);
+ operands[0] = adjust_address (operands[0], HImode, 2);
if (! CONSTANT_P(operands[2]))
{
if (REG_P (operands[2]))
operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
else
- operands[2] = adj_offsettable_operand(operands[2], 2);
+ operands[2] = adjust_address (operands[2], HImode, 2);
output_asm_insn (\"bic %2, %0\", operands);
output_asm_insn (\"bic %2, %0\", lateoperands);
if (REG_P (operands[0]))
operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
else
- operands[0] = adj_offsettable_operand (operands[0], 2);
+ operands[0] = adjust_address (operands[0], HImode, 2);
if (! CONSTANT_P(operands[2]))
{
if (REG_P (operands[2]))
operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
else
- operands[2] = adj_offsettable_operand (operands[2], 2);
+ operands[2] = adjust_address (operands[2], HImode, 2);
output_asm_insn (\"bis %2, %0\", operands);
output_asm_insn (\"bis %2, %0\", lateoperands);
case MEM:
if (GET_CODE (XEXP (x, 0)) != PRE_DEC
&& GET_CODE (XEXP (x, 0)) != POST_INC)
- x = adj_offsettable_operand (x, 4);
+ x = adjust_address (x, SImode, 4);
print_operand_address (stream, XEXP (x, 0));
break;
default:
fprintf (file, reg_names[REGNO (x) + 1]);
break;
case MEM:
- x = XEXP (adj_offsettable_operand (x, 4), 0);
+ x = XEXP (adjust_address (x, SImode, 4), 0);
print_operand_address (file, x);
if (GET_CODE (x) == CONST_INT)
fprintf (file, "[r0]");
;; Machine description for GNU compiler, Vax Version
-;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000
+;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000, 2001
;; Free Software Foundation, Inc.
;; This file is part of GNU CC.
}
else
operands[0]
- = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
+ = adjust_address (operands[0],
+ INTVAL (operands[1]) == 8 ? QImode : HImode,
+ INTVAL (operands[2]) / 8);
CC_STATUS_INIT;
if (INTVAL (operands[1]) == 8)
}
else
operands[1]
- = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
+ = adjust_address (operands[1],
+ INTVAL (operands[2]) == 8 ? QImode : HImode,
+ INTVAL (operands[3]) / 8);
if (INTVAL (operands[2]) == 8)
return \"movzbl %1,%0\";
}
else
operands[1]
- = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
+ = adjust_address (operands[1],
+ INTVAL (operands[2]) == 8 ? QImode : HImode,
+ INTVAL (operands[3]) / 8);
if (INTVAL (operands[2]) == 8)
return \"cvtbl %1,%0\";
/* Subroutines for insn-output.c for AT&T we32000 Family.
- Copyright (C) 1991, 1992, 1997, 1998, 1999, 2000
+ Copyright (C) 1991, 1992, 1997, 1998, 1999, 2000, 2001
Free Software Foundation, Inc.
Contributed by John Wehle (john@feith1.uucp)
msw_dreg = operands[0];
}
else if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
- lsw_operands[0] = adj_offsettable_operand (operands[0], 4);
+ lsw_operands[0] = adjust_address (operands[0], SImode, 4);
else
abort ();
}
else if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
{
- lsw_operands[1] = adj_offsettable_operand (operands[1], 4);
+ lsw_operands[1] = adjust_address (operands[1], SImode, 4);
lsw_sreg = operands[1];
for ( ; ; )
{
if (GET_CODE (operands[0]) == REG)
lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
- lsw_operands[0] = adj_offsettable_operand (operands[0], 4);
+ lsw_operands[0] = adjust_address (operands[0], SImode, 4);
else if (GET_CODE (operands[0]) == CONST_DOUBLE)
{
lsw_operands[0] = GEN_INT (CONST_DOUBLE_HIGH (operands[0]));
;; Machine description for GNU compiler, AT&T we32000 Version
-;; Copyright (C) 1991, 1992, 1994, 1998, 1999 Free Software Foundation, Inc.
+;; Copyright (C) 1991, 1992, 1994, 1998, 1999, 2001
+;; Free Software Foundation, Inc.
;; Contributed by John Wehle (john@feith1.uucp)
;; This file is part of GNU CC.
lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
- lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
+ lsw_operands[0] = adjust_address (operands[0], SImode, 4);
else
abort();
lsw_operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
else
if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
- lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
+ lsw_operands[2] = adjust_address (operands[2], SImode, 4);
else
if (GET_CODE (operands[2]) == CONST_DOUBLE)
{
lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
- lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
+ lsw_operands[0] = adjust_address(operands[0], SImode, 4);
else
abort();
lsw_operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
- lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
+ lsw_operands[1] = adjust_address (operands[1], SImode, 4);
else
if (GET_CODE (operands[1]) == CONST_DOUBLE)
{
lsw_operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
else
if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
- lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
+ lsw_operands[2] = adjust_address (operands[2], SImode, 4);
else
if (GET_CODE (operands[2]) == CONST_DOUBLE)
{
lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
- lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
+ lsw_operands[0] = adjust_address (operands[0], SImode, 4);
else
abort();
lsw_operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
else
if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
- lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
+ lsw_operands[2] = adjust_address (operands[2], SImode, 4);
else
if (GET_CODE (operands[2]) == CONST_DOUBLE)
{
lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
- lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
+ lsw_operands[0] = adjust_address (operands[0], SImode, 4);
else
abort();
lsw_operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
- lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
+ lsw_operands[1] = adjust_address (operands[1], SImode, 4);
else
if (GET_CODE (operands[1]) == CONST_DOUBLE)
{
lsw_operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
else
if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
- lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
+ lsw_operands[2] = adjust_address (operands[2], SImode, 4);
else
if (GET_CODE (operands[2]) == CONST_DOUBLE)
{
register HOST_WIDE_INT c;
{
register RTX_CODE code;
+ rtx y = x;
register enum machine_mode mode;
register rtx tem;
int all_constant = 0;
x = XEXP (x, 0);
goto restart;
}
- else if (CONSTANT_P (XEXP (x, 0)))
+ else if (CONSTANT_P (XEXP (x, 1)))
{
- x = gen_rtx_PLUS (mode,
- plus_constant (XEXP (x, 0), c),
- XEXP (x, 1));
+ x = gen_rtx_PLUS (mode, XEXP (x, 0), plus_constant (XEXP (x, 1), c));
c = 0;
}
- else if (CONSTANT_P (XEXP (x, 1)))
+ else if (find_constant_term_loc (&y))
{
- x = gen_rtx_PLUS (mode,
- XEXP (x, 0),
- plus_constant (XEXP (x, 1), c));
+ /* We need to be careful since X may be shared and we can't
+ modify it in place. */
+ rtx copy = copy_rtx (x);
+ rtx *const_loc = find_constant_term_loc (©);
+
+ *const_loc = plus_constant (*const_loc, c);
+ x = copy;
c = 0;
}
break;
static void validate_replace_rtx_1 PARAMS ((rtx *, rtx, rtx, rtx));
static rtx *find_single_use_1 PARAMS ((rtx, rtx *));
-static rtx *find_constant_term_loc PARAMS ((rtx *));
static void validate_replace_src_1 PARAMS ((rtx *, void *));
static rtx split_insn PARAMS ((rtx));
return the location (type rtx *) of the pointer to that constant term.
Otherwise, return a null pointer. */
-static rtx *
+rtx *
find_constant_term_loc (p)
rtx *p;
{
lose: ATTRIBUTE_UNUSED_LABEL
return 0;
}
-
-/* Given an operand OP that is a valid memory reference which
- satisfies offsettable_memref_p, return a new memory reference whose
- address has been adjusted by OFFSET. OFFSET should be positive and
- less than the size of the object referenced. */
-
-rtx
-adj_offsettable_operand (op, offset)
- rtx op;
- int offset;
-{
- register enum rtx_code code = GET_CODE (op);
-
- if (code == MEM)
- {
- register rtx y = XEXP (op, 0);
- register rtx new;
-
- if (CONSTANT_ADDRESS_P (y))
- {
- new = gen_rtx_MEM (GET_MODE (op), plus_constant (y, offset));
- MEM_COPY_ATTRIBUTES (new, op);
- return new;
- }
-
- if (GET_CODE (y) == PLUS)
- {
- rtx z = y;
- register rtx *const_loc;
-
- op = copy_rtx (op);
- z = XEXP (op, 0);
- const_loc = find_constant_term_loc (&z);
- if (const_loc)
- {
- *const_loc = plus_constant (*const_loc, offset);
- return op;
- }
- }
-
- new = gen_rtx_MEM (GET_MODE (op), plus_constant (y, offset));
- MEM_COPY_ATTRIBUTES (new, op);
- return new;
- }
- abort ();
-}
\f
/* Like extract_insn, but save insn extracted and don't extract again, when
called again for the same insn expecting that recog_data still contain the
extern rtx follow_jumps PARAMS ((rtx));
/* In recog.c */
-extern rtx adj_offsettable_operand PARAMS ((rtx, int));
+extern rtx *find_constant_term_loc PARAMS ((rtx *));
/* In emit-rtl.c */
extern rtx try_split PARAMS ((rtx, rtx, int));
projects / gcc.git / commitdiff