+2015-08-25 Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR target/67344
+ * config/rs6000/rs6000.md (*and<mode>3_imm_dot_shifted): Change to
+ a define_insn, remove second alternative.
+
2015-08-25 Thomas Schwinge <thomas@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_insn_and_split "*and<mode>3_imm_dot_shifted"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+(define_insn "*and<mode>3_imm_dot_shifted"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC
(and:GPR
- (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 4 "const_int_operand" "n,n"))
- (match_operand:GPR 2 "const_int_operand" "n,n"))
+ (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
+ (match_operand:SI 4 "const_int_operand" "n"))
+ (match_operand:GPR 2 "const_int_operand" "n"))
(const_int 0)))
- (clobber (match_scratch:GPR 0 "=r,r"))]
+ (clobber (match_scratch:GPR 0 "=r"))]
"logical_const_operand (GEN_INT (UINTVAL (operands[2])
<< INTVAL (operands[4])),
DImode)
&& rs6000_gen_cell_microcode"
{
operands[2] = GEN_INT (UINTVAL (operands[2]) << INTVAL (operands[4]));
- if (which_alternative == 0)
- return "andi%e2. %0,%1,%u2";
- else
- return "#";
+ return "andi%e2. %0,%1,%u2";
}
- "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
- [(set (match_dup 0)
- (and:GPR (lshiftrt:GPR (match_dup 1)
- (match_dup 4))
- (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- ""
[(set_attr "type" "logical")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
+ (set_attr "dot" "yes")])
(define_insn "and<mode>3_mask"