add extra "persistence" bit to svremap instruction

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index 0556ca34886af707e210cd7e752c7714e45ab9b1..8ad064cabf6bfde0cb38e9d5272a5b46cd289b8c 100644 (file)
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -42,17 +42,20 @@ Special Registers Altered:
 
 SVRM-Form
 
-* svremap SVme, mi0, mi1, mi2, mo0, mo1
+* svremap SVme, mi0, mi1, mi2, mo0, mo1, pst
 
 Pseudo-code:
 
-    # place into SVREMAP SPR
-    SVSTATE[42:46] <- SVme
+    # registers RA RB RC RT EA/FRS SVSHAPE0-3 indices
     SVSTATE[32:33] <- mi0
     SVSTATE[34:35] <- mi1
     SVSTATE[36:37] <- mi2
     SVSTATE[38:39] <- mo0
     SVSTATE[40:41] <- mo1
+    # enable bit for RA RB RC RT EA/FRS
+    SVSTATE[42:46] <- SVme
+    # persistence bit (applies to more than one instruction)
+    SVSTATE[62] <- pst
 
 Special Registers Altered:
 

diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index 5c2bb828c139d76f29e99082d8a7ecb36319194d..f1ba11efb1372c13d1a24337ccd9f53bd0003c74 100644 (file)
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -280,8 +280,8 @@
    | PO   |  SVxd   |   SVyd | SVzd | SVRM |vf |   XO |  / |
 
 # 1.6.34 SVRM-FORM
-   |0     |6     |11  |13   |15   |17   |19   |21    |26     |31 |
-   | PO   | SVme |mi0 | mi1 | mi2 | mo0 | mo1 | rsvd | XO    | / |
+   |0     |6     |11  |13   |15   |17   |19   |21  |22   |26     |31 |
+   | PO   | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |///  | XO    | / |
 
 # 1.6.28 Instruction Fields
     A (6)
@@ -633,6 +633,10 @@
         Field used to specify preferred sign for BCD opera-
         tions.
         Formats: VX
+    pst (21)
+        Field used in REMAP to indicate "persistence" mode (REMAP
+        continues to apply to multiple instructions)
+        Formats: SVRM
     PT (28:31)
         Immediate field used to specify a 4-bit unsigned
         value.

diff --git a/src/openpower/decoder/isa/svstate.py b/src/openpower/decoder/isa/svstate.py
index 6127b25b716ef26f15f99af80fd00d1bb5923110..3ad12a777fea1c8ec0e6fa8d576505c22a8ed7cc 100644 (file)
--- a/src/openpower/decoder/isa/svstate.py
+++ b/src/openpower/decoder/isa/svstate.py
@@ -112,3 +112,19 @@ class SVP64State(SelectableInt):
     def SVme(self, value):
         self.fsi['SVme'].eq(value)
 
+    @property
+    def vfirst(self):
+        return self.fsi['vfirst'].asint(msb0=True)
+
+    @vfirst.setter
+    def vfirst(self, value):
+        self.fsi['vfirst'].eq(value)
+
+    @property
+    def RMpst(self):
+        return self.fsi['RMpst'].asint(msb0=True)
+
+    @RMpst.setter
+    def RMpst(self, value):
+        self.fsi['RMpst'].eq(value)
+

diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py
index d86338f276d1ff7af9a6236ed49ac256900cd339..317e34222af8673739cf847e873b475f5809e926 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_setvl.py
+++ b/src/openpower/decoder/isa/test_caller_setvl.py
@@ -331,26 +331,28 @@ class DecoderTestCase(FHDLTestCase):
     def test_svremap(self):
         """svremap, see if values get set
         """
-        lst = SVP64Asm(["svremap 11, 0, 1, 2, 3, 3",
+        lst = SVP64Asm(["svremap 11, 0, 1, 2, 3, 3, 1",
                         ])
         lst = list(lst)
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program)
-            svremap = sim.svstate
-            print ("SVREMAP after", bin(svremap.value))
-            print ("        men", bin(svremap.SVme))
-            print ("        mi0", bin(svremap.mi0))
-            print ("        mi1", bin(svremap.mi1))
-            print ("        mi2", bin(svremap.mi2))
-            print ("        mo0", bin(svremap.mo0))
-            print ("        mo1", bin(svremap.mo1))
-            self.assertEqual(svremap.SVme, 11)
-            self.assertEqual(svremap.mi0, 0)
-            self.assertEqual(svremap.mi1, 1)
-            self.assertEqual(svremap.mi2, 2)
-            self.assertEqual(svremap.mo0, 3)
-            self.assertEqual(svremap.mo1, 3)
+            svstate = sim.svstate
+            print ("SVREMAP after", bin(svstate.value))
+            print ("        men", bin(svstate.SVme))
+            print ("        mi0", bin(svstate.mi0))
+            print ("        mi1", bin(svstate.mi1))
+            print ("        mi2", bin(svstate.mi2))
+            print ("        mo0", bin(svstate.mo0))
+            print ("        mo1", bin(svstate.mo1))
+            print ("    persist", bin(svstate.RMpst))
+            self.assertEqual(svstate.SVme, 11)
+            self.assertEqual(svstate.mi0, 0)
+            self.assertEqual(svstate.mi1, 1)
+            self.assertEqual(svstate.mi2, 2)
+            self.assertEqual(svstate.mo0, 3)
+            self.assertEqual(svstate.mo1, 3)
+            self.assertEqual(svstate.RMpst, 1)
 
     def run_tst_program(self, prog, initial_regs=None,
                               svstate=None):

diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py
index 191d0ce23d67df9e8a6df8b12ebad145a510ac99..bbfe084586e21a3af1da8780e2db2172e6e5be1f 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_fft.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py
@@ -133,7 +133,7 @@ class FFTTestCase(FHDLTestCase):
 
     def test_sv_remap_fpmadds_fft(self):
         """>>> lst = ["svshape 8, 1, 1, 1, 0",
-                     "svremap 31, 1, 0, 2, 0, 1",
+                     "svremap 31, 1, 0, 2, 0, 1, 0",
                       "sv.ffmadds 2.v, 2.v, 2.v, 10.v"
                      ]
             runs a full in-place O(N log2 N) butterfly schedule for
@@ -149,7 +149,7 @@ class FFTTestCase(FHDLTestCase):
             (3 inputs, 2 outputs)
         """
         lst = SVP64Asm( ["svshape 8, 1, 1, 1, 0",
-                         "svremap 31, 1, 0, 2, 0, 1",
+                         "svremap 31, 1, 0, 2, 0, 1, 0",
                         "sv.ffmadds 0.v, 0.v, 0.v, 8.v"
                         ])
         lst = list(lst)
@@ -195,7 +195,7 @@ class FFTTestCase(FHDLTestCase):
     def test_sv_remap_fpmadds_fft_svstep(self):
         """>>> lst = SVP64Asm( [
                             "svshape 8, 1, 1, 1, 1",
-                             "svremap 31, 1, 0, 2, 0, 1",
+                             "svremap 31, 1, 0, 2, 0, 1, 0",
                             "sv.ffmadds 0.v, 0.v, 0.v, 8.v",
                             "setvl. 0, 0, 1, 1, 0, 0",
                             "bc 4, 2, -16"
@@ -210,7 +210,7 @@ class FFTTestCase(FHDLTestCase):
         """
         lst = SVP64Asm( [
                         "svshape 8, 1, 1, 1, 1",
-                         "svremap 31, 1, 0, 2, 0, 1",
+                         "svremap 31, 1, 0, 2, 0, 1, 0",
                         "sv.ffmadds 0.v, 0.v, 0.v, 8.v",
                         "setvl. 0, 0, 1, 1, 0, 0",
                         "bc 4, 2, -16"
@@ -279,10 +279,10 @@ class FFTTestCase(FHDLTestCase):
         """>>> lst = SVP64Asm( [
                         "svshape 8, 1, 1, 1, 1",
                          # RA: jh (S1) RB: n/a RC: k (S2) RT: scalar EA: n/a
-                         "svremap 5, 1, 0, 2, 0, 0",
+                         "svremap 5, 1, 0, 2, 0, 0, 1",
                          "sv.fmuls 24, 0.v, 8.v",
                          # RA: scal RB: jl (S0) RC: n/a RT: jl (S0) EA: jh (S1)
-                         "svremap 26, 0, 0, 0, 0, 1",
+                         "svremap 26, 0, 0, 0, 0, 1, 1",
                         "sv.ffadds 0.v, 24, 0.v",
                         "setvl. 0, 0, 1, 1, 0, 0",
                         "bc 4, 2, -28"
@@ -311,10 +311,10 @@ class FFTTestCase(FHDLTestCase):
         lst = SVP64Asm( [
                         "svshape 8, 1, 1, 1, 1",
                          # RA: jh (S1) RB: n/a RC: k (S2) RT: scalar EA: n/a
-                         "svremap 5, 1, 0, 2, 0, 0",
+                         "svremap 5, 1, 0, 2, 0, 0, 1",
                          "sv.fmuls 24, 0.v, 8.v",
                          # RA: scal RB: jl (S0) RC: n/a RT: jl (S0) EA: jh (S1)
-                         "svremap 26, 0, 0, 0, 0, 1",
+                         "svremap 26, 0, 0, 0, 0, 1, 1",
                         "sv.ffadds 0.v, 24, 0.v",
                         "setvl. 0, 0, 1, 1, 0, 0",
                         "bc 4, 2, -28"
@@ -515,22 +515,22 @@ class FFTTestCase(FHDLTestCase):
                         # set triple butterfly mode
                         "svshape 8, 1, 1, 1, 1",
                         # tpre
-                        "svremap 5, 1, 0, 2, 0, 0",
+                        "svremap 5, 1, 0, 2, 0, 0, 1",
                         "sv.fmuls 24, 0.v, 16.v",    # mul1_r = r*cos_r
-                        "svremap 5, 1, 0, 2, 0, 0",
+                        "svremap 5, 1, 0, 2, 0, 0, 1",
                         "sv.fmadds 24, 8.v, 20.v, 24", # mul2_r = i*sin_i
                                                      # tpre = mul1_r + mul2_r
                         # tpim
-                         "svremap 5, 1, 0, 2, 0, 0",
+                         "svremap 5, 1, 0, 2, 0, 0, 1",
                         "sv.fmuls 26, 0.v, 20.v",    # mul1_i = r*sin_i
-                         "svremap 5, 1, 0, 2, 0, 0",
+                         "svremap 5, 1, 0, 2, 0, 0, 1",
                         "sv.fmsubs 26, 8.v, 16.v, 26", # mul2_i = i*cos_r
                                                      # tpim = mul2_i - mul1_i
                         # vec_r jh/jl
-                         "svremap 26, 0, 0, 0, 0, 1",
+                         "svremap 26, 0, 0, 0, 0, 1, 1",
                         "sv.ffadds 0.v, 24, 0.v",    # vh/vl +/- tpre
                         # vec_i jh/jl
-                         "svremap 26, 0, 0, 0, 0, 1",
+                         "svremap 26, 0, 0, 0, 0, 1, 1",
                         "sv.ffadds 8.v, 26, 8.v",    # vh/vl +- tpim
 
                         # svstep loop

diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index accbcd68dc7983f33bfa4a9a50d824b77a11911b..6a37ce4db3c37a62ca8b1cad3aeaf6ee69428c9c 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -28,13 +28,13 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_sv_remap1(self):
         """>>> lst = ["svshape 2, 2, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0",
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
                        "sv.fmadds 0.v, 8.v, 16.v, 0.v"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
         lst = SVP64Asm(["svshape 2, 2, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0",
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
                        "sv.fmadds 0.v, 16.v, 32.v, 0.v"
                         ])
         lst = list(lst)
@@ -94,13 +94,13 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_sv_remap2(self):
         """>>> lst = ["svshape 5, 4, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0",
+                        "svremap 31, 1, 2, 3, 0, 0, 0, 0",
                        "sv.fmadds 0.v, 8.v, 16.v, 0.v"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
         lst = SVP64Asm(["svshape 4, 3, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0",
+                        "svremap 31, 1, 2, 3, 0, 0, 0, 0",
                        "sv.fmadds 0.v, 16.v, 32.v, 0.v"
                         ])
         lst = list(lst)

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index b36ae32198c57512c619b9500e46930a85dd4576..6ea5009af1b316595a20e5910b3f6e15ffcbc482 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -223,6 +223,7 @@ class SVP64Asm:
             insn |= fields[3] << (31-16) # mi2        , bits 15-16
             insn |= fields[4] << (31-18) # m00        , bits 17-18
             insn |= fields[5] << (31-20) # m01        , bits 19-20
+            insn |= fields[6] << (31-21) # m01        , bit 21
             insn |= 0b00010   << (31-30) # XO       , bits 26..30
             #insn &= ((1<<32)-1)
             log ("svremap", bin(insn))
@@ -1001,7 +1002,7 @@ if __name__ == '__main__':
     lst = [
              #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
              #'sv.ffadds 0.v, 8.v, 4.v',
-             #'svremap 11, 0, 1, 2, 3, 2',
+             'svremap 11, 0, 1, 2, 3, 2, 1',
              'svshape 8, 1, 1, 1, 0',
              'svshape 8, 1, 1, 1, 1',
             ]