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Fix PLL code
authorJean THOMAS <git0@pub.jeanthomas.me>
Fri, 26 Jun 2020 13:19:06 +0000 (15:19 +0200)
committerJean THOMAS <git0@pub.jeanthomas.me>
Fri, 26 Jun 2020 13:19:06 +0000 (15:19 +0200)
gram/simulation/simcrg.py patch | blob | history

diff --git a/gram/simulation/simcrg.py b/gram/simulation/simcrg.py
index 400d47915790252ed16f00565e608f681f72e8a5..12b713ad681868d8162da8f4e3b16eab36f334bf 100644 (file)
--- a/gram/simulation/simcrg.py
+++ b/gram/simulation/simcrg.py
@@ -48,7 +48,7 @@ class PLL(Elaboratable):
                        p_FEEDBK_PATH='CLKOP',
                        #p_FREQUENCY_PIN_CLKOP='200',
                        i_CLKI=self.clkin,
-                       #i_CLKFB=clkfb,
+                       i_CLKFB=clkfb,
                        i_RST=0,
                        i_STDBY=0,
                        i_PHASESEL0=0,