software/bios/memtest: add data bus test (0xAAAAAAAA, 0x55555555) on a small portion...

we now need to add another random addressing test to avoid linear access on L2 cache

diff --git a/software/bios/sdram.c b/software/bios/sdram.c
index 785dcde37dd7fa3f11c548b6a978fbb8d4ae5d80..2ca55da6e26b0ce84d5a77aba4aa2a7a20ee3c8c 100644 (file)
--- a/software/bios/sdram.c
+++ b/software/bios/sdram.c
@@ -424,6 +424,9 @@ int sdrlevel(void)
 
 #define TEST_SIZE (2*1024*1024)
 
+#define ONEZERO 0xAAAAAAAA
+#define ZEROONE 0x55555555
+
 int memtest_silent(void)
 {
        volatile unsigned int *array = (unsigned int *)SDRAM_BASE;
@@ -431,15 +434,26 @@ int memtest_silent(void)
        unsigned int prv;
        unsigned int error_cnt;
 
-       for(i=0;i<TEST_SIZE/4;i++) {
-               array[i] = 0x5A5A5A5A;
+       /* test data bus */
+       for(i=0;i<128;i++) {
+               array[i] = ONEZERO;
        }
        error_cnt = 0;
-       for(i=0;i<TEST_SIZE/4;i++) {
-               if(array[i] != 0x5A5A5A5A)
+       for(i=0;i<128;i++) {
+               if(array[i] != ONEZERO)
+                       error_cnt++;
+       }
+
+       for(i=0;i<128;i++) {
+               array[i] = ZEROONE;
+       }
+       error_cnt = 0;
+       for(i=0;i<128;i++) {
+               if(array[i] != ZEROONE)
                        error_cnt++;
        }
 
+       /* test random data */
        prv = 0;
        for(i=0;i<TEST_SIZE/4;i++) {
                prv = 1664525*prv + 1013904223;