radeonsi/gfx9: move RW_BUFFERS from s[0:1] to s[8:9] for HS and GS

Let's use the same user data SGPRs in all stages.
(for SPI_SHADER_USER_DATA_COMMON_0)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index cda7d944c8d67977625b38d54ec3607f97600c3d..9ba8df602c5f009812cabe6f1daf2fc445f28cee 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1980,32 +1980,16 @@ static void si_emit_global_shader_pointers(struct si_context *sctx,
                               R_00B030_SPI_SHADER_USER_DATA_PS_0);
        si_emit_shader_pointer(sctx, descs,
                               R_00B130_SPI_SHADER_USER_DATA_VS_0);
+       si_emit_shader_pointer(sctx, descs,
+                              R_00B330_SPI_SHADER_USER_DATA_ES_0);
 
        if (sctx->b.chip_class >= GFX9) {
                /* GFX9 merged LS-HS and ES-GS. */
-               if (descs == &sctx->descriptors[SI_DESCS_RW_BUFFERS]) {
-                       /* Set RW_BUFFERS in the special registers, so that
-                        * it's preloaded into s[0:1] instead of s[8:9].
-                        */
-                       si_emit_shader_pointer(sctx, descs,
-                                              R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS);
-                       si_emit_shader_pointer(sctx, descs,
-                                              R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS);
-               } else {
-                       /* Set BINDLESS_SAMPLERS_AND_IMAGES into s[10:11],
-                        * s[8:9] remains unused for now.
-                        */
-                       assert(descs == &sctx->bindless_descriptors);
-                       si_emit_shader_pointer(sctx, descs,
-                                              R_00B330_SPI_SHADER_USER_DATA_ES_0);
-                       si_emit_shader_pointer(sctx, descs,
-                                              R_00B430_SPI_SHADER_USER_DATA_LS_0);
-               }
+               si_emit_shader_pointer(sctx, descs,
+                                      R_00B430_SPI_SHADER_USER_DATA_LS_0);
        } else {
                si_emit_shader_pointer(sctx, descs,
                                       R_00B230_SPI_SHADER_USER_DATA_GS_0);
-               si_emit_shader_pointer(sctx, descs,
-                                      R_00B330_SPI_SHADER_USER_DATA_ES_0);
                si_emit_shader_pointer(sctx, descs,
                                       R_00B430_SPI_SHADER_USER_DATA_HS_0);
                si_emit_shader_pointer(sctx, descs,

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 4456c3dab3f85a7f46f25e56f7bc71027d9f82d2..62a056dce4365452d5365445150a785cfbfd8bdc 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3031,11 +3031,13 @@ static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
 {
        LLVMValueRef ret = ctx->return_value;
 
-       ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers, 0);
        ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
        ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
        ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
        ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
+
+       ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
+                                          8 + SI_SGPR_RW_BUFFERS);
        ret = si_insert_input_ptr_as_2xi32(ctx, ret,
                ctx->param_bindless_samplers_and_images,
                8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
@@ -3072,11 +3074,12 @@ static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
 {
        LLVMValueRef ret = ctx->return_value;
 
-       ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers, 0);
        ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
        ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
-
        ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
+
+       ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
+                                          8 + SI_SGPR_RW_BUFFERS);
        ret = si_insert_input_ptr_as_2xi32(ctx, ret,
                ctx->param_bindless_samplers_and_images,
                8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
@@ -4437,8 +4440,8 @@ static void create_function(struct si_shader_context *ctx)
 
        case SI_SHADER_MERGED_VERTEX_TESSCTRL:
                /* Merged stages have 8 system SGPRs at the beginning. */
-               ctx->param_rw_buffers = /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
-                       add_arg(&fninfo, ARG_SGPR, si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
+               add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
+               add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_HI_HS */
                ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
                ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
                ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
@@ -4446,12 +4449,7 @@ static void create_function(struct si_shader_context *ctx)
                add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
                add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
 
-               add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
-               add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
-
-               ctx->param_bindless_samplers_and_images =
-                       add_arg(&fninfo, ARG_SGPR, si_const_array(ctx->v8i32, 0));
-
+               declare_global_desc_pointers(ctx, &fninfo);
                declare_per_stage_desc_pointers(ctx, &fninfo,
                                                ctx->type == PIPE_SHADER_VERTEX);
                declare_vs_specific_input_sgprs(ctx, &fninfo);
@@ -4495,8 +4493,8 @@ static void create_function(struct si_shader_context *ctx)
 
        case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
                /* Merged stages have 8 system SGPRs at the beginning. */
-               ctx->param_rw_buffers = /* SPI_SHADER_USER_DATA_ADDR_LO_GS */
-                       add_arg(&fninfo, ARG_SGPR, si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
+               add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_LO_GS) */
+               add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_HI_GS) */
                ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
                ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
                ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
@@ -4504,12 +4502,7 @@ static void create_function(struct si_shader_context *ctx)
                add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
                add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
 
-               add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
-               add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
-
-               ctx->param_bindless_samplers_and_images =
-                       add_arg(&fninfo, ARG_SGPR, si_const_array(ctx->v8i32, 0));
-
+               declare_global_desc_pointers(ctx, &fninfo);
                declare_per_stage_desc_pointers(ctx, &fninfo,
                                                (ctx->type == PIPE_SHADER_VERTEX ||
                                                 ctx->type == PIPE_SHADER_TESS_EVAL));