uart2csr: add pads parameter

diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py
index 0582762aa643e648413b03d673debf311b3bca05..617399ef58a6e34992ac6e7e5a63f4e3d15feb33 100644 (file)
--- a/examples/de0_nano/top.py
+++ b/examples/de0_nano/top.py
@@ -58,10 +58,7 @@ class SoC(Module):
                self.submodules.mila = MiLa(mila_width, mila_depth, [term], rle=True)
        
                # Uart2Csr
-               self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200)
-               uart_pads = platform.request("serial")
-               self.comb += uart_pads.tx.eq(self.uart2csr.tx)
-               self.comb += self.uart2csr.rx.eq(uart_pads.rx)
+               self.submodules.uart2csr = uart2csr.Uart2Csr(platform.request("serial"), clk_freq, 115200)
        
                # Csr Interconnect
                self.submodules.csrbankarray = csrgen.BankArray(self,

diff --git a/miscope/com/uart2csr/__init__.py b/miscope/com/uart2csr/__init__.py
index e8e569ce5f5ec0f74c219eea8434c384b096adbf..3f97ad3efd09154c6da597fa7918ad04ecd3e88d 100644 (file)
--- a/miscope/com/uart2csr/__init__.py
+++ b/miscope/com/uart2csr/__init__.py
@@ -10,10 +10,7 @@ READ_CMD = 0x02
 CLOSE_CMD = 0x03
 
 class Uart2Csr(Module):
-       def __init__(self, clk_freq, baud):
-               # Uart interface
-               self.rx = Signal()
-               self.tx = Signal()
+       def __init__(self, pads, clk_freq, baud):
                
                # Csr interface
                self.csr = csr.Interface()
@@ -27,8 +24,8 @@ class Uart2Csr(Module):
                # In/Out
                #
                self.comb +=[
-                       uart.rx.eq(self.rx),
-                       self.tx.eq(uart.tx)
+                       uart.rx.eq(pads.rx),
+                       pads.tx.eq(uart.tx)
                ]
 
                cmd = Signal(8)