"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
-(define_insn ""
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (compare:CCFP
- (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
- (const_int 0))
- (match_operand:SF 2 "gpc_reg_operand" "f")
- (match_operand:SF 3 "gpc_reg_operand" "f"))
- (const_int 0)))
- (clobber (match_scratch:SF 4 "=f"))]
- "TARGET_PPCFPX"
- "fsel. %4,%1,%2,%3"
- [(set_attr "type" "fp")])
-
-(define_insn ""
- [(set (match_operand:CCFP 4 "cc_reg_operand" "=y")
- (compare:CCFP
- (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
- (const_int 0))
- (match_operand:SF 2 "gpc_reg_operand" "f")
- (match_operand:SF 3 "gpc_reg_operand" "f"))
- (const_int 0)))
- (set (match_operand:SF 0 "gpc_reg_operand" "=f")
- (if_then_else:SF (ge (match_dup 1) (const_int 0))
- (match_dup 2)
- (match_dup 3)))]
- "TARGET_PPCFPX"
- "fsel. %0,%1,%2,%3"
- [(set_attr "type" "fp")])
-
(define_insn "negdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_PPCFPX || TARGET_POWER2"
"fsqrt %0,%1"
[(set_attr "type" "dsqrt")])
+
;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a fsel
;; instruction and some auxiliary computations. Then we just have a single
;; DEFINE_INSN for fsel and the define_splits to make them if made by
;; combine.
+
(define_expand "maxdf3"
[(set (match_dup 3)
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
"TARGET_PPCFPX"
"
{ operands[3] = gen_reg_rtx (DFmode); }")
+
(define_split
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
(match_dup 1)
(match_dup 2)))]
"")
+
(define_expand "mindf3"
[(set (match_dup 3)
(minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
"TARGET_PPCFPX"
"
{ operands[3] = gen_reg_rtx (DFmode); }")
+
(define_split
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
(match_dup 1)
(match_dup 2)))]
"")
+
(define_insn ""
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
"TARGET_PPCFPX"
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
-(define_insn ""
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (compare:CCFP
- (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
- (const_int 0))
- (match_operand:DF 2 "gpc_reg_operand" "f")
- (match_operand:DF 3 "gpc_reg_operand" "f"))
- (const_int 0)))
- (clobber (match_scratch:DF 4 "=f"))]
- "TARGET_PPCFPX"
- "fsel. %4,%1,%2,%3"
- [(set_attr "type" "fp")])
-(define_insn ""
- [(set (match_operand:CCFP 4 "cc_reg_operand" "=y")
- (compare:CCFP
- (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
- (const_int 0))
- (match_operand:DF 2 "gpc_reg_operand" "f")
- (match_operand:DF 3 "gpc_reg_operand" "f"))
- (const_int 0)))
- (set (match_operand:DF 0 "gpc_reg_operand" "=f")
- (if_then_else:DF (ge (match_dup 1) (const_int 0))
- (match_dup 2)
- (match_dup 3)))]
- "TARGET_PPCFPX"
- "fsel. %0,%1,%2,%3"
- [(set_attr "type" "fp")])
\f
;; Conversions to and from floating-point.
(define_expand "floatsidf2"