Allow POs to be PIs in XAIG

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index e93fd35f7f13b7c6b0e5b6c8b8cb141c0ee9dc95..a881b1b88930e549a4b5136ca56276c494cea886 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -161,12 +161,8 @@ struct XAigerWriter
                        }
                }
 
-               for (auto bit : input_bits) {
-                       if (!bit.wire->port_output)
-                               undriven_bits.erase(bit);
-                       // Erase POs that are also PIs
-                       output_bits.erase(bit);
-               }
+               for (auto bit : input_bits)
+                       undriven_bits.erase(bit);
 
                for (auto bit : output_bits)
                        if (!bit.wire->port_input)
@@ -275,7 +271,8 @@ struct XAigerWriter
                                                }
                                        }
                                }
-                               if (!abc_box_seen) abc_box_seen = inst_module->attributes.count("\\abc_box_id");
+                               if (!abc_box_seen)
+                                       abc_box_seen = inst_module->attributes.count("\\abc_box_id");
 
                                ff_bits.emplace_back(d, q);
                                undriven_bits.erase(q);