intel/disasm: Fix decoding of src0 of SENDS

There is no instruction field for the register file for src0 because
it's always GRF.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 7d821dbc1faa5ae6a6a29798056f07e20bcb1abf..31d932b9cbab946f9f2bbb6034ee23c8b323f68a 100644 (file)
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1446,7 +1446,7 @@ src0(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
          return src_sends_da(file,
                              devinfo,
                              BRW_REGISTER_TYPE_UD,
-                             brw_inst_send_src0_reg_file(devinfo, inst),
+                             BRW_GENERAL_REGISTER_FILE,
                              brw_inst_src0_da_reg_nr(devinfo, inst),
                              brw_inst_src0_da16_subreg_nr(devinfo, inst));
       } else {