adds the sscaled formats, this passes some more of the draw-vertices tests.
}
static int eg_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
- uint32_t stride, uint32_t format)
+ uint32_t stride, uint32_t src_format)
{
struct radeon_state *vs_resource = &rctx->vs_resource[id];
struct r600_screen *rscreen = rctx->screen;
+ unsigned format, num_format = 0, format_comp = 0;
+
+ format = r600_translate_colorformat(src_format);
+ r600_translate_vertex_num_format(src_format, &num_format, &format_comp);
+ format = S_030008_DATA_FORMAT(format) | S_030008_NUM_FORMAT_ALL(num_format) |
+ S_030008_FORMAT_COMP_ALL(format_comp);
+
radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
radeon_ws_bo_reference(rscreen->rw, &vs_resource->bo[0], rbuffer->bo);
vs_resource->nbo = 1;
vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD0] = offset;
vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->size - offset - 1;
- vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = S_030008_STRIDE(stride) |
- S_030008_DATA_FORMAT(format);
+ vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = S_030008_STRIDE(stride) | format;
vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
case PIPE_FORMAT_R32_FLOAT:
return V_028C70_COLOR_32_FLOAT;
+ case PIPE_FORMAT_R16G16_FLOAT:
+ return V_028C70_COLOR_16_16_FLOAT;
+
+ case PIPE_FORMAT_R16G16_SSCALED:
+ return V_028C70_COLOR_16_16;
+
+ case PIPE_FORMAT_R16G16B16_FLOAT:
+ return V_028C70_COLOR_16_16_16_16_FLOAT;
+
/* 64-bit buffers. */
+ case PIPE_FORMAT_R16G16B16A16_SSCALED:
+ case PIPE_FORMAT_R16G16B16_SSCALED:
case PIPE_FORMAT_R16G16B16A16_UNORM:
case PIPE_FORMAT_R16G16B16A16_SNORM:
return V_028C70_COLOR_16_16_16_16;
case PIPE_FORMAT_R32G32_FLOAT:
return V_028C70_COLOR_32_32_FLOAT;
+ case PIPE_FORMAT_R32G32_SSCALED:
+ return V_028C70_COLOR_32_32;
+
/* 128-bit buffers. */
case PIPE_FORMAT_R32G32B32_FLOAT:
return V_028C70_COLOR_32_32_32_FLOAT;
}
}
+static INLINE void r600_translate_vertex_num_format(enum pipe_format format, uint32_t *num_format_p,
+ uint32_t *format_comp_p)
+{
+ uint32_t num_format = 0, format_comp = 0;
+ switch (format) {
+ case PIPE_FORMAT_R16G16B16A16_SSCALED:
+ case PIPE_FORMAT_R16G16B16_SSCALED:
+ case PIPE_FORMAT_R16G16_SSCALED:
+ case PIPE_FORMAT_R32G32_SSCALED:
+ num_format = V_030008_SQ_NUM_FORMAT_SCALED;
+ format_comp = 1;
+ break;
+ default:
+ break;
+ }
+ *num_format_p = num_format;
+ *format_comp_p = format_comp;
+}
+
static INLINE boolean r600_is_sampler_format_supported(enum pipe_format format)
{
return r600_translate_texformat(format, NULL, NULL, NULL) != ~0;
#define S_030008_NUM_FORMAT_ALL(x) (((x) & 0x3) << 26)
#define G_030008_NUM_FORMAT_ALL(x) (((x) >> 26) & 0x3)
#define C_030008_NUM_FORMAT_ALL 0xF3FFFFFF
+#define V_030008_SQ_NUM_FORMAT_NORM 0x00000000
+#define V_030008_SQ_NUM_FORMAT_INT 0x00000001
+#define V_030008_SQ_NUM_FORMAT_SCALED 0x00000002
#define S_030008_FORMAT_COMP_ALL(x) (((x) & 0x1) << 28)
#define G_030008_FORMAT_COMP_ALL(x) (((x) >> 28) & 0x1)
#define C_030008_FORMAT_COMP_ALL 0xEFFFFFFF
vertex_buffer = &rctx->vertex_buffer[j];
rbuffer = (struct r600_resource*)vertex_buffer->buffer;
offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
- format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
- rctx->vtbl->vs_resource(rctx, i, rbuffer, offset, vertex_buffer->stride, format);
+ rctx->vtbl->vs_resource(rctx, i, rbuffer, offset, vertex_buffer->stride, rctx->vertex_elements->elements[i].src_format);
radeon_draw_bind(&rctx->draw, vs_resource);
}
rctx->vs_nresource = rctx->vertex_elements->count;
}
static int r600_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
- uint32_t stride, uint32_t format)
+ uint32_t stride, uint32_t src_format)
{
struct radeon_state *vs_resource = &rctx->vs_resource[id];
struct r600_screen *rscreen = rctx->screen;
+ unsigned format, num_format = 0, format_comp = 0;
+ format = r600_translate_colorformat(src_format);
+
+ r600_translate_vertex_num_format(src_format, &num_format, &format_comp);
+
+ format = S_038008_DATA_FORMAT(format) | S_038008_NUM_FORMAT_ALL(num_format) | S_038008_FORMAT_COMP_ALL(format_comp);
+
radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
radeon_ws_bo_reference(rscreen->rw, &vs_resource->bo[0], rbuffer->bo);
vs_resource->nbo = 1;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->size - offset - 1;
- vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(stride) |
- S_038008_DATA_FORMAT(format);
+ vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(stride) | format;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
case PIPE_FORMAT_R32_FLOAT:
return V_0280A0_COLOR_32_FLOAT;
+
case PIPE_FORMAT_R16G16_FLOAT:
- case PIPE_FORMAT_R16G16B16_FLOAT:
- return V_0280A0_COLOR_16_16_16_16_FLOAT;
+ return V_0280A0_COLOR_16_16_FLOAT;
+
+ case PIPE_FORMAT_R16G16_SSCALED:
+ return V_0280A0_COLOR_16_16;
+
/* 64-bit buffers. */
+ case PIPE_FORMAT_R16G16B16_SSCALED:
+ case PIPE_FORMAT_R16G16B16A16_SSCALED:
case PIPE_FORMAT_R16G16B16A16_UNORM:
case PIPE_FORMAT_R16G16B16A16_SNORM:
return V_0280A0_COLOR_16_16_16_16;
+
+ case PIPE_FORMAT_R16G16B16_FLOAT:
case PIPE_FORMAT_R16G16B16A16_FLOAT:
return V_0280A0_COLOR_16_16_16_16_FLOAT;
+
case PIPE_FORMAT_R32G32_FLOAT:
return V_0280A0_COLOR_32_32_FLOAT;
+ case PIPE_FORMAT_R32G32_SSCALED:
+ return V_0280A0_COLOR_32_32;
+
/* 128-bit buffers. */
case PIPE_FORMAT_R32G32B32_FLOAT:
return V_0280A0_COLOR_32_32_32_FLOAT;
case PIPE_FORMAT_UYVY:
case PIPE_FORMAT_YUYV:
default:
- R600_ERR("unsupported color format %d\n", format);
+ R600_ERR("unsupported color format %d %s\n", format, util_format_name(format));
return ~0; /* Unsupported. */
}
}
+static INLINE void r600_translate_vertex_num_format(enum pipe_format format, uint32_t *num_format_p,
+ uint32_t *format_comp_p)
+{
+ uint32_t num_format = 0, format_comp = 0;
+ switch (format) {
+ case PIPE_FORMAT_R16G16B16A16_SSCALED:
+ case PIPE_FORMAT_R16G16B16_SSCALED:
+ case PIPE_FORMAT_R16G16_SSCALED:
+ case PIPE_FORMAT_R32G32_SSCALED:
+ num_format = V_038008_SQ_NUM_FORMAT_SCALED;
+ format_comp = 1;
+ break;
+ default:
+ break;
+ }
+ *num_format_p = num_format;
+ *format_comp_p = format_comp;
+}
+
static INLINE boolean r600_is_sampler_format_supported(enum pipe_format format)
{
return r600_translate_texformat(format, NULL, NULL, NULL) != ~0;
#define S_038008_NUM_FORMAT_ALL(x) (((x) & 0x3) << 26)
#define G_038008_NUM_FORMAT_ALL(x) (((x) >> 26) & 0x3)
#define C_038008_NUM_FORMAT_ALL 0xF3FFFFFF
+#define V_038008_SQ_NUM_FORMAT_NORM 0x00000000
+#define V_038008_SQ_NUM_FORMAT_INT 0x00000001
+#define V_038008_SQ_NUM_FORMAT_SCALED 0x00000002
#define S_038008_FORMAT_COMP_ALL(x) (((x) & 0x1) << 28)
#define G_038008_FORMAT_COMP_ALL(x) (((x) >> 28) & 0x1)
#define C_038008_FORMAT_COMP_ALL 0xEFFFFFFF