#include "base/remote_gdb.hh"
#include "base/socket.hh"
#include "base/trace.hh"
+#include "cpu/decode.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/GDBAcc.hh"
// User was stopped at pc, e.g. the instruction at pc was not
// executed.
MachInst inst = read<MachInst>(pc.pc());
- StaticInstPtr si(inst, pc.pc());
+ StaticInstPtr si = context->getDecoderPtr()->decode(inst, pc.pc());
if (si->hasBranchTarget(pc, context, bpc)) {
// Don't bother setting a breakpoint on the taken branch if it
// is the same as the next pc
#include "base/remote_gdb.hh"
#include "base/socket.hh"
#include "base/trace.hh"
+#include "cpu/decode.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
// User was stopped at pc, e.g. the instruction at pc was not
// executed.
MachInst inst = read<MachInst>(pc.pc());
- StaticInstPtr si(inst, pc.pc());
+ StaticInstPtr si = context->getDecoderPtr()->decode(inst, pc.pc());
if (si->hasBranchTarget(pc, context, bpc)) {
// Don't bother setting a breakpoint on the taken branch if it
// is the same as the next pc
Source('activity.cc')
Source('base.cc')
Source('cpuevent.cc')
+Source('decode.cc')
Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
--- /dev/null
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "cpu/decode.hh"
+
+DecodeCache<TheISA::decodeInst> Decoder::cache;
--- /dev/null
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __CPU_DECODE_HH__
+#define __CPU_DECODE_HH__
+
+#include "arch/isa_traits.hh"
+#include "arch/types.hh"
+#include "config/the_isa.hh"
+#include "cpu/decode_cache.hh"
+#include "cpu/static_inst.hh"
+
+/// The decoder class. This class doesn't do much of anything now, but in the
+/// future it will be redefinable per ISA and allow more interesting behavior.
+class Decoder
+{
+ protected:
+ /// A cache of decoded instruction objects.
+ static DecodeCache<TheISA::decodeInst> cache;
+
+ public:
+ /// Decode a machine instruction.
+ /// @param mach_inst The binary instruction to decode.
+ /// @retval A pointer to the corresponding StaticInst object.
+ StaticInstPtr
+ decode(TheISA::ExtMachInst mach_inst, Addr addr)
+ {
+ return cache.decode(mach_inst, addr);
+ }
+};
+
+#endif // __CPU_DECODE_HH__
--- /dev/null
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __CPU_DECODE_CACHE_HH__
+#define __CPU_DECODE_CACHE_HH__
+
+#include "arch/isa_traits.hh"
+#include "arch/types.hh"
+#include "base/hashmap.hh"
+#include "config/the_isa.hh"
+#include "cpu/static_inst.hh"
+
+typedef StaticInstPtr (*DecodeInstFunc)(TheISA::ExtMachInst);
+
+template <DecodeInstFunc decodeInstFunc>
+class DecodeCache
+{
+ private:
+ typedef TheISA::ExtMachInst ExtMachInst;
+
+ /// Hash of decoded instructions.
+ typedef m5::hash_map<ExtMachInst, StaticInstPtr> InstMap;
+ InstMap instMap;
+
+ /// A table of instructions which are already been decoded, indexed by
+ /// page offset.
+ class DecodePage
+ {
+ protected:
+ StaticInstPtr instructions[TheISA::PageBytes];
+
+ // A helper function to compute the index of an address in the table.
+ Addr offset(Addr addr) { return addr & (TheISA::PageBytes - 1); }
+
+ public:
+ /// Decode the given instruction. First attempt to find it in the
+ /// table, then in the generic decode cache, and finally call the
+ /// actual decode function.
+ ///
+ /// @param mach_inst The predecoded instruction to decode.
+ /// @param addr The address the instruction came from.
+ /// @param cache A cache of already decoded instructions.
+ /// @retval The decoded instruction object.
+ StaticInstPtr
+ decode(const ExtMachInst &mach_inst, Addr addr, InstMap &instMap)
+ {
+ StaticInstPtr si = instructions[offset(addr)];
+ if (si && (si->machInst == mach_inst)) {
+ return si;
+ }
+
+ InstMap::iterator iter = instMap.find(mach_inst);
+ if (iter != instMap.end()) {
+ si = iter->second;
+ } else {
+ si = decodeInstFunc(mach_inst);
+ instMap[mach_inst] = si;
+ }
+
+ instructions[offset(addr)] = si;
+ return si;
+ }
+ };
+
+ /// A store of DecodePages. Basically a slightly smarter hash_map.
+ class DecodePages
+ {
+ protected:
+ typedef typename m5::hash_map<Addr, DecodePage *> PageMap;
+ typedef typename PageMap::iterator PageIt;
+ PageIt recent[2];
+ PageMap pageMap;
+
+ /// Update the small cache of recent lookups.
+ /// @param recentest The most recent result;
+ void
+ update(PageIt recentest)
+ {
+ recent[1] = recent[0];
+ recent[0] = recentest;
+ }
+
+ public:
+ /// Constructor
+ DecodePages()
+ {
+ recent[0] = recent[1] = pageMap.end();
+ }
+
+ /// Attempt to find the DecodePage which goes with a particular
+ /// address. First check the small cache of recent results, then
+ /// actually look in the hash_map.
+ /// @param addr The address to look up.
+ DecodePage *
+ findPage(Addr addr)
+ {
+ Addr page_addr = addr & ~(TheISA::PageBytes - 1);
+
+ // Check against recent lookups.
+ if (recent[0] != pageMap.end()) {
+ if (recent[0]->first == page_addr)
+ return recent[0]->second;
+ if (recent[1] != pageMap.end() &&
+ recent[1]->first == page_addr) {
+ update(recent[1]);
+ // recent[1] has just become recent[0].
+ return recent[0]->second;
+ }
+ }
+
+ // Actually look in the has_map.
+ PageIt it = pageMap.find(page_addr);
+ if (it != pageMap.end()) {
+ update(it);
+ return it->second;
+ }
+
+ // Didn't find it so return NULL.
+ return NULL;
+ }
+
+ void
+ addPage(Addr addr, DecodePage *page)
+ {
+ Addr page_addr = addr & ~(TheISA::PageBytes - 1);
+ typename PageMap::value_type to_insert(page_addr, page);
+ update(pageMap.insert(to_insert).first);
+ }
+ } decodePages;
+
+ public:
+ /// Decode a machine instruction.
+ /// @param mach_inst The binary instruction to decode.
+ /// @retval A pointer to the corresponding StaticInst object.
+ StaticInstPtr
+ decode(ExtMachInst mach_inst, Addr addr)
+ {
+ // Try to find a matching address based table of instructions.
+ DecodePage *page = decodePages.findPage(addr);
+ if (!page) {
+ // Nothing was found, so create a new one.
+ page = new DecodePage;
+ decodePages.addPage(addr, page);
+ }
+
+ // Use the table to decode the instruction. It will fall back to other
+ // mechanisms if it needs to.
+ return page->decode(mach_inst, addr, instMap);
+ }
+};
+
+#endif // __CPU_DECODE_CACHE_HH__
return dtb_res->tlb();
}
+Decoder *
+InOrderCPU::getDecoderPtr()
+{
+ FetchUnit *fetch_res =
+ dynamic_cast<FetchUnit*>(resPool->getResource(fetchPortIdx));
+ return &fetch_res->decoder;
+}
+
Fault
InOrderCPU::read(DynInstPtr inst, Addr addr,
uint8_t *data, unsigned size, unsigned flags)
TheISA::TLB *getITBPtr();
TheISA::TLB *getDTBPtr();
+ Decoder *getDecoderPtr();
+
/** Accessor Type for the SkedCache */
typedef uint32_t SkedID;
}
void
-InOrderDynInst::setMachInst(ExtMachInst machInst)
+InOrderDynInst::setStaticInst(StaticInstPtr si)
{
- staticInst = StaticInst::decode(machInst, pc.instAddr());
+ staticInst = si;
for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
_destRegIdx[i] = this->staticInst->destRegIdx(i);
std::string instName()
{ return (staticInst) ? staticInst->getName() : "undecoded-inst"; }
- void setMachInst(ExtMachInst inst);
+ void setStaticInst(StaticInstPtr si);
ExtMachInst getMachInst() { return staticInst->machInst; }
ext_inst = predecoder[tid]->getExtMachInst(instPC);
inst->pcState(instPC);
- inst->setMachInst(ext_inst);
+ inst->setStaticInst(decoder.decode(ext_inst, instPC.instAddr()));
}
void
#include "arch/predecoder.hh"
#include "arch/tlb.hh"
#include "config/the_isa.hh"
+#include "cpu/decode.hh"
#include "cpu/inorder/resources/cache_unit.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_traits.hh"
void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ Decoder decoder;
+
private:
void squashCacheRequest(CacheReqPtr req_ptr);
/** @TODO: PERF: Should we bind this to a pointer in constructor? */
TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
+ Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
+
System *getSystemPtr() { return cpu->system; }
/** Returns a pointer to this CPU. */
#include "arch/sparc/utility.hh"
#include "base/socket.hh"
#include "cpu/base.hh"
+#include "cpu/decode.hh"
#include "cpu/legiontrace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
PCState tempPC = pc;
StaticInstPtr legionInst =
- StaticInst::decode(predecoder.getExtMachInst(tempPC),
- lgnPc);
+ thread->getDecoderPtr()->decode(
+ predecoder.getExtMachInst(tempPC), lgnPc);
outs << setfill(' ') << setw(15)
<< " Legion Inst: "
<< "0x" << setw(8) << setfill('0') << hex
#include "arch/utility.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
+#include "cpu/decode.hh"
#include "cpu/pc_event.hh"
#include "cpu/timebuf.hh"
#include "cpu/translation.hh"
return (addr & ~(cacheBlkMask));
}
+ /** The decoder. */
+ Decoder decoder;
+
private:
DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
StaticInstPtr curMacroop, TheISA::PCState thisPC,
DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
// We will use a nop in ordier to carry the fault.
DynInstPtr instruction = buildInst(tid,
- StaticInstPtr(TheISA::NoopMachInst, fetchPC.instAddr()),
+ decoder.decode(TheISA::NoopMachInst, fetchPC.instAddr()),
NULL, fetchPC, fetchPC, false);
instruction->setPredTarg(fetchPC);
do {
if (!(curMacroop || inRom)) {
if (predecoder.extMachInstReady()) {
- ExtMachInst extMachInst;
-
- extMachInst = predecoder.getExtMachInst(thisPC);
- staticInst = StaticInstPtr(extMachInst,
- thisPC.instAddr());
+ ExtMachInst extMachInst =
+ predecoder.getExtMachInst(thisPC);
+ staticInst =
+ decoder.decode(extMachInst, thisPC.instAddr());
// Increment stat of fetched instructions.
++fetchedInsts;
/** Returns a pointer to the DTB. */
TheISA::TLB *getDTBPtr() { return cpu->dtb; }
+ Decoder *getDecoderPtr() { return &cpu->fetch.decoder; }
+
/** Returns a pointer to this CPU. */
virtual BaseCPU *getCpuPtr() { return cpu; }
stayAtPC = false;
ExtMachInst machInst = predecoder.getExtMachInst(pcState);
thread->pcState(pcState);
- instPtr = StaticInst::decode(machInst, pcState.instAddr());
+ instPtr = thread->decoder.decode(machInst, pcState.instAddr());
} else {
stayAtPC = true;
fetchOffset += sizeof(MachInst);
#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
+#include "cpu/decode.hh"
#include "cpu/pc_event.hh"
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh"
+#include "cpu/decode.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
#include "debug/FloatRegs.hh"
TheISA::TLB *itb;
TheISA::TLB *dtb;
+ Decoder decoder;
+
// constructor: initialize SimpleThread from given process structure
#if FULL_SYSTEM
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
TheISA::TLB *getDTBPtr() { return dtb; }
+ Decoder *getDecoderPtr() { return &decoder; }
+
System *getSystemPtr() { return system; }
#if FULL_SYSTEM
StaticInstPtr StaticInst::nullStaticInstPtr;
-// Define the decode cache hash map.
-StaticInst::DecodeCache StaticInst::decodeCache;
-StaticInst::AddrDecodeCache StaticInst::addrDecodeCache;
-StaticInst::cacheElement StaticInst::recentDecodes[2];
-
using namespace std;
StaticInst::~StaticInst()
delete cachedDisassembly;
}
-void
-StaticInst::dumpDecodeCacheStats()
-{
- cerr << "Decode hash table stats @ " << curTick() << ":" << endl;
- cerr << "\tnum entries = " << decodeCache.size() << endl;
- cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl;
- vector<int> hist(100, 0);
- int max_hist = 0;
- for (int i = 0; i < decodeCache.bucket_count(); ++i) {
- int count = decodeCache.elems_in_bucket(i);
- if (count > max_hist)
- max_hist = count;
- hist[count]++;
- }
- for (int i = 0; i <= max_hist; ++i) {
- cerr << "\tbuckets of size " << i << " = " << hist[i] << endl;
- }
-}
-
bool
StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
TheISA::PCState &tgt) const
#include <bitset>
#include <string>
-#include "arch/isa_traits.hh"
#include "arch/registers.hh"
#include "arch/types.hh"
-#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/refcnt.hh"
#include "base/types.hh"
class TimingSimpleCPU;
class InorderCPU;
class SymbolTable;
-class AddrDecodePage;
namespace Trace {
class InstRecord;
class StaticInst : public StaticInstBase
{
public:
-
- /// Binary machine instruction type.
- typedef TheISA::MachInst MachInst;
/// Binary extended machine instruction type.
typedef TheISA::ExtMachInst ExtMachInst;
/// Logical register index type.
virtual const std::string &disassemble(Addr pc,
const SymbolTable *symtab = 0) const;
- /// Decoded instruction cache type.
- /// For now we're using a generic hash_map; this seems to work
- /// pretty well.
- typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
-
- /// A cache of decoded instruction objects.
- static DecodeCache decodeCache;
-
- /**
- * Dump some basic stats on the decode cache hash map.
- * Only gets called if DECODE_CACHE_HASH_STATS is defined.
- */
- static void dumpDecodeCacheStats();
-
- /// Decode a machine instruction.
- /// @param mach_inst The binary instruction to decode.
- /// @retval A pointer to the corresponding StaticInst object.
- //This is defined as inlined below.
- static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
-
/// Return name of machine instruction
std::string getName() { return mnemonic; }
-
- /// Decoded instruction cache type, for address decoding.
- /// A generic hash_map is used.
- typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache;
-
- /// A cache of decoded instruction objects from addresses.
- static AddrDecodeCache addrDecodeCache;
-
- struct cacheElement
- {
- Addr page_addr;
- AddrDecodePage *decodePage;
-
- cacheElement() : decodePage(NULL) { }
- };
-
- /// An array of recently decoded instructions.
- // might not use an array if there is only two elements
- static struct cacheElement recentDecodes[2];
-
- /// Updates the recently decoded instructions entries
- /// @param page_addr The page address recently used.
- /// @param decodePage Pointer to decoding page containing the decoded
- /// instruction.
- static inline void
- updateCache(Addr page_addr, AddrDecodePage *decodePage)
- {
- recentDecodes[1].page_addr = recentDecodes[0].page_addr;
- recentDecodes[1].decodePage = recentDecodes[0].decodePage;
- recentDecodes[0].page_addr = page_addr;
- recentDecodes[0].decodePage = decodePage;
- }
-
- /// Searches the decoded instruction cache for instruction decoding.
- /// If it is not found, then we decode the instruction.
- /// Otherwise, we get the instruction from the cache and move it into
- /// the address-to-instruction decoding page.
- /// @param mach_inst The binary instruction to decode.
- /// @param addr The address that contained the binary instruction.
- /// @param decodePage Pointer to decoding page containing the instruction.
- /// @retval A pointer to the corresponding StaticInst object.
- //This is defined as inlined below.
- static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
- AddrDecodePage *decodePage);
};
typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
{
}
- /// Construct directly from machine instruction.
- /// Calls StaticInst::decode().
- explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr)
- : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr))
- {
- }
-
/// Convert to pointer to StaticInstBase class.
operator const StaticInstBasePtr()
{
}
};
-/// A page of a list of decoded instructions from an address.
-class AddrDecodePage
-{
- typedef TheISA::ExtMachInst ExtMachInst;
- protected:
- StaticInstPtr instructions[TheISA::PageBytes];
- bool valid[TheISA::PageBytes];
- Addr lowerMask;
-
- public:
- /// Constructor
- AddrDecodePage()
- {
- lowerMask = TheISA::PageBytes - 1;
- memset(valid, 0, TheISA::PageBytes);
- }
-
- /// Checks if the instruction is already decoded and the machine
- /// instruction in the cache matches the current machine instruction
- /// related to the address
- /// @param mach_inst The binary instruction to check
- /// @param addr The address containing the instruction
- bool
- decoded(ExtMachInst mach_inst, Addr addr)
- {
- return (valid[addr & lowerMask] &&
- (instructions[addr & lowerMask]->machInst == mach_inst));
- }
-
- /// Returns the instruction object. decoded should be called first
- /// to check if the instruction is valid.
- /// @param addr The address of the instruction.
- /// @retval A pointer to the corresponding StaticInst object.
- StaticInstPtr
- getInst(Addr addr)
- {
- return instructions[addr & lowerMask];
- }
-
- /// Inserts a pointer to a StaticInst object into the list of decoded
- /// instructions on the page.
- /// @param addr The address of the instruction.
- /// @param si A pointer to the corresponding StaticInst object.
- void
- insert(Addr addr, StaticInstPtr &si)
- {
- instructions[addr & lowerMask] = si;
- valid[addr & lowerMask] = true;
- }
-};
-
-
-inline StaticInstPtr
-StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
-{
-#ifdef DECODE_CACHE_HASH_STATS
- // Simple stats on decode hash_map. Turns out the default
- // hash function is as good as anything I could come up with.
- const int dump_every_n = 10000000;
- static int decodes_til_dump = dump_every_n;
-
- if (--decodes_til_dump == 0) {
- dumpDecodeCacheStats();
- decodes_til_dump = dump_every_n;
- }
-#endif
-
- Addr page_addr = addr & ~(TheISA::PageBytes - 1);
-
- // checks recently decoded addresses
- if (recentDecodes[0].decodePage &&
- page_addr == recentDecodes[0].page_addr) {
- if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
- return recentDecodes[0].decodePage->getInst(addr);
-
- return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
- }
-
- if (recentDecodes[1].decodePage &&
- page_addr == recentDecodes[1].page_addr) {
- if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
- return recentDecodes[1].decodePage->getInst(addr);
-
- return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
- }
-
- // searches the page containing the address to decode
- AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr);
- if (iter != addrDecodeCache.end()) {
- updateCache(page_addr, iter->second);
- if (iter->second->decoded(mach_inst, addr))
- return iter->second->getInst(addr);
-
- return searchCache(mach_inst, addr, iter->second);
- }
-
- // creates a new object for a page of decoded instructions
- AddrDecodePage *decodePage = new AddrDecodePage;
- addrDecodeCache[page_addr] = decodePage;
- updateCache(page_addr, decodePage);
- return searchCache(mach_inst, addr, decodePage);
-}
-
-inline StaticInstPtr
-StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
- AddrDecodePage *decodePage)
-{
- DecodeCache::iterator iter = decodeCache.find(mach_inst);
- if (iter != decodeCache.end()) {
- decodePage->insert(addr, iter->second);
- return iter->second;
- }
-
- StaticInstPtr si = TheISA::decodeInst(mach_inst);
- decodePage->insert(addr, si);
- decodeCache[mach_inst] = si;
- return si;
-}
-
#endif // __CPU_STATIC_INST_HH__
}
class BaseCPU;
class Checkpoint;
+class Decoder;
class EndQuiesceEvent;
class TranslatingPort;
class FunctionalPort;
virtual TheISA::TLB *getDTBPtr() = 0;
+ virtual Decoder *getDecoderPtr() = 0;
+
virtual System *getSystemPtr() = 0;
#if FULL_SYSTEM
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
+ Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
+
System *getSystemPtr() { return actualTC->getSystemPtr(); }
#if FULL_SYSTEM
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