Linux works, LiteDRAM works (need cleaning, temporary push)

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index d97b68a36009b3b1706d9db07b498bd9c7a4c512..6b9c2c9c540e2a6917d88f323c3e7475a94d0c75 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -46,10 +46,11 @@ class BaseSoC(SoCCore):
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
+        sys_clk_freq = int(50e6)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
-
+        self.add_constant("UART_POLLING",None)
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),

diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v
index cdd1a95e0756030644b6a7f7db44ee5c7964041f..9eb86cb583f34f17b844827668d7ad7298ec5285 100644 (file)
--- a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v
+++ b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v
@@ -171,7 +171,7 @@ bp_chip
        );
 
 
-  bind bp_be_top
+/*  bind bp_be_top
     bp_be_nonsynth_tracer
      #(.cfg_p(cfg_p))
      tracer
@@ -207,7 +207,7 @@ bp_chip
        ,.priv_mode_i(be_mem.csr.priv_mode_n)
        ,.mpp_i(be_mem.csr.mstatus_n.mpp)
        );
-
+*/
 /*bind bp_be_top
   bp_be_nonsynth_perf
    #(.cfg_p(cfg_p))

diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index e9ad416431e24f28a7bec4ce174998ed11b1028f..ccce090c24453627e721feca7b70b1016099a7fe 100644 (file)
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -40,9 +40,9 @@ from litex.soc.cores.cpu import CPU
 CPU_VARIANTS = {
     "standard": "freechips.rocketchip.system.LitexConfig",
 }
-
+# -mcmodel=medany
 GCC_FLAGS = {
-    "standard": "-march=rv64ia   -mabi=lp64 -O0 ",
+    "standard": "-march=rv64ia -mabi=lp64 -O0  ",
 }
 
 class BlackParrotRV64(CPU):
@@ -52,15 +52,15 @@ class BlackParrotRV64(CPU):
     gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
                             "riscv64-none-elf")
     linker_output_format = "elf64-littleriscv"
-    io_regions           = {0x30000000: 0x20000000} # origin, length
-
+    io_regions           = {0x50000000: 0x10000000} # origin, length
+   
     @property
     def mem_map(self):
         return {
-            "ethmac"   : 0x30000000,
-            "csr"      : 0x40000000,
-            "rom"      : 0x50000000,
-            "sram"     : 0x51000000,
+            "csr"      : 0x50000000,
+#            "ethmac"   : 0x55000000,
+            "rom"      : 0x70000000,
+            "sram"     : 0x71000000,
             "main_ram" : 0x80000000,
         }
 
@@ -81,33 +81,33 @@ class BlackParrotRV64(CPU):
         self.idbus        = idbus = wishbone.Interface(data_width=64, adr_width=37)
         self.periph_buses = [idbus]
         self.memory_buses = []
-
-        # # #
+        self.buses     = [wbn]
 
         self.cpu_params = dict(
             # clock, reset
-            i_clk_i      = ClockSignal(),
-            i_reset_i    = ResetSignal() | self.reset,
-
-            # irq
-            i_interrupts = self.interrupt,
-
-            # wishbone
-            i_wbm_dat_i  = idbus.dat_r,
-            o_wbm_dat_o  = idbus.dat_w,
-            i_wbm_ack_i  = idbus.ack,
-            i_wbm_err_i  = 0,
-            i_wbm_rty_i  = 0,
-            o_wbm_adr_o  = idbus.adr,
-            o_wbm_stb_o  = idbus.stb,
-            o_wbm_cyc_o  = idbus.cyc,
-            o_wbm_sel_o  = idbus.sel,
-            o_wbm_we_o   = idbus.we,
-            o_wbm_cti_o  = idbus.cti,
-            o_wbm_bte_o  = idbus.bte,
-        )
-
-        # add verilog sources
+            i_clk_i = ClockSignal(),
+            i_reset_i = ResetSignal() | self.reset,
+            
+            # irq           
+            #i_interrupts = self.interrupt,
+            
+            #wishbone
+            i_wbm_dat_i = wbn.dat_r,
+            o_wbm_dat_o = wbn.dat_w,
+            i_wbm_ack_i = wbn.ack,
+            i_wbm_err_i = wbn.err,
+            #i_wbm_rty_i = 0,
+            o_wbm_adr_o = wbn.adr,
+            o_wbm_stb_o = wbn.stb,
+            o_wbm_cyc_o = wbn.cyc,
+            o_wbm_sel_o = wbn.sel,
+            o_wbm_we_o = wbn.we,
+            o_wbm_cti_o = wbn.cti,
+            o_wbm_bte_o = wbn.bte,
+
+            )
+     
+           # add verilog sources
         self.add_sources(platform, variant)
 
     def set_reset_address(self, reset_address):
@@ -131,7 +131,7 @@ class BlackParrotRV64(CPU):
                     a = os.popen('echo '+ str(dir_))
                     dir_start = a.read()
                     vdir = dir_start[:-1] + line[s2:-1]
-                    print("INCDIR" + vdir)
+                    #print("INCDIR" + vdir)
                     platform.add_verilog_include_path(vdir)  #this line might be changed
                 elif (temp[0]=='$') :
                     s2 = line.find('/')
@@ -139,7 +139,7 @@ class BlackParrotRV64(CPU):
                     a = os.popen('echo '+ str(dir_))
                     dir_start = a.read()
                     vdir = dir_start[:-1]+ line[s2:-1]
-                    print(vdir)
+                    #print(vdir)
                     platform.add_source(vdir) #this line might be changed
                 elif (temp[0] == '/'):
                     assert("No support for absolute path for now")

diff --git a/litex/soc/cores/cpu/blackparrot/flist_litex.verilator b/litex/soc/cores/cpu/blackparrot/flist_litex.verilator
index 65e8e1c4eca25861368244ecfb4ee40570750843..ba656dc14d6a8f643a8049966f5cbd69ea2125d0 100644 (file)
--- a/litex/soc/cores/cpu/blackparrot/flist_litex.verilator
+++ b/litex/soc/cores/cpu/blackparrot/flist_litex.verilator
@@ -203,7 +203,7 @@ $BP_COMMON_DIR/src/v/bp_addr_map.v
 // bsg_ip_cores files
 $BASEJUMP_STL_DIR/bsg_fsb/bsg_fsb_node_trace_replay.v
 // be files
-$BP_BE_DIR/test/common/bp_be_nonsynth_tracer.v
+//$BP_BE_DIR/test/common/bp_be_nonsynth_tracer.v
 // $BP_BE_DIR/test/common/bp_be_nonsynth_perf.v
 // me files
 // $BP_ME_DIR/test/common/bp_mem.v
@@ -218,9 +218,10 @@ $BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v
 // top files
 $BP_TOP_DIR/test/common/bp_nonsynth_host.v
 // $BP_TOP_DIR/test/common/bp_nonsynth_if_verif.v
-$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v
+//$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v
 // /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_top/syn/results/verilator/bp_top_trace_demo.e_bp_single_core_cfg.build/wrapper.v
 // /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_top/syn/results/verilator/bp_top_trace_demo.e_bp_single_core_cfg.build/test_bp.cpp
+$BP_TOP_DIR/test/common/bp_monitor.cpp
 $BP_FPGA_DIR/bp2wb_convertor.v
 $BP_FPGA_DIR/ExampleBlackParrotSystem.v
 $BP_FPGA_DIR/bsg_mem_1rw_sync_mask_write_bit.v

diff --git a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
index d818ec52b9647bd0bcee418f6479cdb9adb037af..079bb17f79b28e6f42d631a7d09f87333838f09c 100755 (executable)
--- a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
+++ b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
@@ -38,7 +38,8 @@ export SYSTEMC_INCLUDE=$BP_EXTERNAL_DIR/include
 export SYSTEMC_LIBDIR=$BP_EXTERNAL_DIR/lib-linux64
 
 ## Add external tools and libraries to environment
-export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR:$LD_LIBRARY_PATH
+export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR
+#:$LD_LIBRARY_PATH
 #export PATH=$(BP_EXTERNAL_DIR)/bin:$(PATH)
 #export SYN_PATH=$(BP_TOP_DIR)/syn
 #export TB_PATH=$(BP_TOP_DIR)/test/tb

diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile
index cc3b973aa5d2c73bc5ad5302b7776fa19b10ae17..98dc44d52dac763128742761d53e09d053899d07 100755 (executable)
--- a/litex/soc/software/bios/Makefile
+++ b/litex/soc/software/bios/Makefile
@@ -2,7 +2,7 @@ include ../include/generated/variables.mak
 include $(SOC_DIRECTORY)/software/common.mak
 
 ifeq ($(CPU),blackparrot)
-BP_LIBS  = -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/8.3.0
+BP_LIBS =  -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/9.2.0/ 
 BP_FLAGS = -lgcc
 endif
 # Permit TFTP_SERVER_PORT override from shell environment / command line

diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c
index 08b3be4a8ad061a4d4f800e2fe6cb83f8b4bedfa..274cd789fc86c16ffd4f1628f7fb67b0e36ddbab 100644 (file)
--- a/litex/soc/software/bios/boot.c
+++ b/litex/soc/software/bios/boot.c
@@ -32,6 +32,8 @@
 #include "sfl.h"
 #include "boot.h"
 
+#define MEMTEST_DATA_SIZE2 (589824*4)
+
 extern void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr);
 
 static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr)
@@ -59,7 +61,16 @@ static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, u
        mtspr(SPR_EVBAR, addr);
        addr += 0x100;
 #endif
-
+          
+
+/*        volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE;
+        int i;
+        unsigned int rdata;
+        for(i=0;i<MEMTEST_DATA_SIZE2/4;i++) {
+                rdata = array[i];
+                printf("[data 0x%0x]: 0x%08x\n",i,rdata);
+         }
+*/
        boot_helper(r1, r2, r3, addr);
        while(1);
 }

diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 513a1266516e1480ca30583738a9f3d0067f8e2b..7798d301347a7e0b2aa3c1cde6b1dd685f138515 100644 (file)
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -1005,7 +1005,7 @@ int memtest(void)
                return 0;
        else {
                printf("Memtest OK\n");
-               memspeed();
+               //memspeed();
                return 1;
        }
 }

diff --git a/litex/soc/software/include/base/ctype.h b/litex/soc/software/include/base/ctype.h
index 6936859338ea4710bc565ab9b037039bdee7fc20..7542e44022238e050c12ee9ce4098ba3c25e6cfc 100644 (file)
--- a/litex/soc/software/include/base/ctype.h
+++ b/litex/soc/software/include/base/ctype.h
@@ -26,7 +26,11 @@ extern const unsigned char _ctype[];
 #define isalnum(c)     ((__ismask(c)&(_U|_L|_D)) != 0)
 #define isalpha(c)     ((__ismask(c)&(_U|_L)) != 0)
 #define iscntrl(c)     ((__ismask(c)&(_C)) != 0)
-#define isdigit(c)     ((__ismask(c)&(_D)) != 0)
+//#define isdigit(c)   ((__ismask(c)&(_D)) != 0)
+static int isdigit(char c){
+  if ((c>='0') && (c<='9')) return 1;
+    return 0;
+}
 #define isgraph(c)     ((__ismask(c)&(_P|_U|_L|_D)) != 0)
 #define islower(c)     ((__ismask(c)&(_L)) != 0)
 #define isprint(c)     ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0)

diff --git a/litex/soc/software/libbase/libc.c b/litex/soc/software/libbase/libc.c
index be48cf6518861022932015db2a9394bb9a1b047a..698ec59cced2d8ea23774173f9eb5235c8656209 100644 (file)
--- a/litex/soc/software/libbase/libc.c
+++ b/litex/soc/software/libbase/libc.c
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <limits.h>
 #include <inet.h>
-
+#include <errno.h>
 /**
  * strchr - Find the first occurrence of a character in a string
  * @s: The string to be searched
@@ -375,7 +375,7 @@ void *memchr(const void *s, int c, size_t n)
  * @base: The number base to use
  */
 unsigned long strtoul(const char *nptr, char **endptr, int base)
-{
+{       printf("HI\n");
        unsigned long result = 0,value;
 
        if (!base) {
@@ -392,11 +392,14 @@ unsigned long strtoul(const char *nptr, char **endptr, int base)
                if (nptr[0] == '0' && toupper(nptr[1]) == 'X')
                        nptr += 2;
        }
+        printf("HI2\n");
        while (isxdigit(*nptr) &&
               (value = isdigit(*nptr) ? *nptr-'0' : toupper(*nptr)-'A'+10) < base) {
                result = result*base + value;
                nptr++;
+                printf("HI4\n");
        }
+        printf("HI3\n");
        if (endptr)
                *endptr = (char *)nptr;
        return result;

diff --git a/litex/soc/software/libnet/tftp.c b/litex/soc/software/libnet/tftp.c
index 439b3e075006a5f62fd97a2a0660c8f8303f5c53..d5110738821aa7e39de6dbfe0b7469a0c9467b32 100644 (file)
--- a/litex/soc/software/libnet/tftp.c
+++ b/litex/soc/software/libnet/tftp.c
@@ -117,10 +117,11 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
        int i;
        int length_before;
        int spin = 0;
+        printf("DEBUGWTH?\n");
 
        if(!microudp_arp_resolve(ip))
                return -1;
-
+        printf("DEBUG0\n");
        microudp_set_callback(rx_callback);
 
        dst_buffer = buffer;
@@ -129,6 +130,8 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
        transfer_finished = 0;
        tries = 5;
        while(1) {
+                
+                printf("DEBUG1\n");
                packet_data = microudp_get_tx_buffer();
                len = format_request(packet_data, TFTP_RRQ, filename);
                microudp_send(PORT_IN, server_port, len);
@@ -136,6 +139,8 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
                        microudp_service();
                        if((total_length > 0) || transfer_finished) break;
                }
+
+                printf("DEBUG2\n");
                if((total_length > 0) || transfer_finished) break;
                tries--;
                if(tries == 0) {
@@ -144,6 +149,7 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
                }
        }
 
+        printf("DEBUG3\n");
        i = 12000000;
        length_before = total_length;
        while(!transfer_finished) {
@@ -162,8 +168,10 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
                microudp_service();
        }
 
+        printf("DEBUG4\n");
        microudp_set_callback(NULL);
 
+        printf("DEBUG5\n");
        return total_length;
 }
 

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 987681d33e73c8beb148301f92b09851d7645b4b..ebba204bd7ad6b9a819c42530bbf056e9c8bdef8 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -177,6 +177,7 @@ class SimSoC(SoCSDRAM):
             ident               = "LiteX Simulation", ident_version=True,
             l2_reverse          = False,
             **kwargs)
+        self.add_constant("UART_POLLING",None)
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request("sys_clk"))
 
@@ -353,7 +354,7 @@ def main():
         sdram_init     = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness),
         **soc_kwargs)
     if args.ram_init is not None:
-        soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
+        soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000)
     if args.with_ethernet:
         for i in range(4):
             soc.add_constant("LOCALIP{}".format(i+1), int(args.local_ip.split(".")[i]))