-- for conversion from non-pipelined wishbone to pipelined
signal wb_sddma_stb_sent : std_ulogic;
- -- Control/status
- signal core_alt_reset : std_ulogic;
-
-- Status LED
- signal led0_b_pwm : std_ulogic;
- signal led0_r_pwm : std_ulogic;
- signal led0_g_pwm : std_ulogic;
+ signal led_b_pwm : std_ulogic_vector(3 downto 0);
+ signal led_r_pwm : std_ulogic_vector(3 downto 0);
+ signal led_g_pwm : std_ulogic_vector(3 downto 0);
-- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise
signal pwm_counter : std_ulogic_vector(8 downto 0);
pll_locked_out => system_clk_locked
);
- led0_b_pwm <= '1';
- led0_r_pwm <= '1';
- led0_g_pwm <= '0';
+ led_b_pwm <= "1111";
+ led_r_pwm <= "1111";
+ led_g_pwm <= "0000";
- core_alt_reset <= '0';
-- Vivado barfs on those differential signals if left
-- unconnected. So instanciate a diff. buffer and feed