gas/

2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.h (CpuPNI): Removed.
	(CpuUnknownFlags): Replace CpuPNI with CpuSSE3.
	* config/tc-i386.c (md_assemble): Likewise.

include/opcode/

2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Replace CpuPNI with CpuSSE3.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index cfdef0528c8eaa7bfd41fe83c17c2321276b7099..92cbfcd285d22ad0bf4f189dab73f150a0806b3e 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.h (CpuPNI): Removed.
+       (CpuUnknownFlags): Replace CpuPNI with CpuSSE3.
+       * config/tc-i386.c (md_assemble): Likewise.
+
 2006-11-08  Alan Modra  <amodra@bigpond.net.au>
 
        * symbols.c (symbol_create, symbol_clone): Don't set udata.p.

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 758fb22bf03cde565f15163f0e0ddc8f569ca145..767e7e3bd056729c373c99eb67aa7e854785937e 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1854,9 +1854,9 @@ md_assemble (line)
     {
       expressionS *exp;
 
-      if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
+      if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
        {
-         /* These Intel Prescott New Instructions have the fixed
+         /* Streaming SIMD extensions 3 Instructions have the fixed
             operands with an opcode suffix which is coded in the same
             place as an 8-bit immediate field would be. Here we check
             those operands and remove them afterwards.  */

diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h
index d0893f90f6f730754633f9a2e1cb95efda87cbe9..0d42e1b86f27e81fbffe0a7f21b0b4f3d88b8dcd 100644 (file)
--- a/gas/config/tc-i386.h
+++ b/gas/config/tc-i386.h
@@ -183,7 +183,6 @@ typedef struct
 #define Cpu3dnow       0x2000  /* 3dnow! support required */
 #define Cpu3dnowA      0x4000  /* 3dnow!Extensions support required */
 #define CpuSSE3               0x8000   /* Streaming SIMD extensions 3 required */
-#define CpuPNI       CpuSSE3   /* Prescott New Instructions required */
 #define CpuPadLock    0x10000  /* VIA PadLock required */
 #define CpuSVME              0x20000   /* AMD Secure Virtual Machine Ext-s required */
 #define CpuVMX       0x40000   /* VMX Instructions required */
@@ -197,7 +196,7 @@ typedef struct
 
   /* The default value for unknown CPUs - enable all features to avoid problems.  */
 #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
-       |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
+       |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
        |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuABM|CpuSSE4a)
 
   /* the bits in opcode_modifier are used to generate the final opcode from

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index f9b98feacd63092f4be1a21e9b879f409f5d07c4..aad0ddbb4e405a7ed3f3daeb93067fe978e5a79b 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
+
 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 
        * score-inst.h (enum score_insn_type): Add Insn_internal.

diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index bbecf3c7adaa08d9ede902fb7a8cc3a365813341..3e91aa0e410d8458753dbc6367e6988592ed40d5 100644 (file)
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -1328,38 +1328,38 @@ static const template i386_optab[] =
 {"punpckhqdq",2, 0x660f6d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
 {"punpcklqdq",2, 0x660f6c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
 
-/* Prescott New Instructions.  */
-
-{"addsubpd",  2, 0x660fd0,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"addsubps",  2, 0xf20fd0,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpxchg16b",1, 0x0fc7,    1, CpuPNI|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} },
-{"fisttp",    1, 0xdf,      1, CpuPNI, sl_FP|Modrm,    { ShortMem|LongMem, 0, 0} },
-{"fisttp",    1, 0xdd,      1, CpuPNI, q_FP|Modrm,     { LLongMem, 0, 0} },
-{"fisttpll",  1, 0xdd,      1, CpuPNI, FP|Modrm,       { LLongMem, 0, 0} },
-{"haddpd",    2, 0x660f7c,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"haddps",    2, 0xf20f7c,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"hsubpd",    2, 0x660f7d,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"hsubps",    2, 0xf20f7d,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"lddqu",     2, 0xf20ff0,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
-{"monitor",   0, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt,   { 0, 0, 0} },
+/* SSE-3 instructions.  */
+
+{"addsubpd",  2, 0x660fd0,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"addsubps",  2, 0xf20fd0,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpxchg16b",1, 0x0fc7,    1, CpuSSE3|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} },
+{"fisttp",    1, 0xdf,      1, CpuSSE3, sl_FP|Modrm,   { ShortMem|LongMem, 0, 0} },
+{"fisttp",    1, 0xdd,      1, CpuSSE3, q_FP|Modrm,    { LLongMem, 0, 0} },
+{"fisttpll",  1, 0xdd,      1, CpuSSE3, FP|Modrm,      { LLongMem, 0, 0} },
+{"haddpd",    2, 0x660f7c,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"haddps",    2, 0xf20f7c,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubpd",    2, 0x660f7d,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubps",    2, 0xf20f7d,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"lddqu",     2, 0xf20ff0,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { LLongMem, RegXMM, 0 } },
+{"monitor",   0, 0x0f01, 0xc8, CpuSSE3, NoSuf|ImmExt,  { 0, 0, 0} },
 /* monitor is very special. CX and DX are always 64bits with zero upper
    32bits in 64bit mode, and 32bits in 16bit and 32bit modes. The
    address size override prefix can be used to overrride the AX size in
    all modes.  */
 /* Need to ensure only "monitor %eax/%ax,%ecx,%edx" is accepted. */
-{"monitor",   3, 0x0f01, 0xc8, CpuPNI|CpuNo64, NoSuf|ImmExt,   { Reg16|Reg32, Reg32, Reg32 } },
+{"monitor",   3, 0x0f01, 0xc8, CpuSSE3|CpuNo64, NoSuf|ImmExt,  { Reg16|Reg32, Reg32, Reg32 } },
 /* Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted. */
-{"monitor",   3, 0x0f01, 0xc8, CpuPNI|Cpu64, NoSuf|ImmExt|NoRex64,     { Reg32|Reg64, Reg64, Reg64 } },
-{"movddup",   2, 0xf20f12,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"movshdup",  2, 0xf30f16,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"movsldup",  2, 0xf30f12,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"mwait",     0, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt,   { 0, 0, 0} },
+{"monitor",   3, 0x0f01, 0xc8, CpuSSE3|Cpu64, NoSuf|ImmExt|NoRex64,    { Reg32|Reg64, Reg64, Reg64 } },
+{"movddup",   2, 0xf20f12,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"movshdup",  2, 0xf30f16,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"movsldup",  2, 0xf30f12,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"mwait",     0, 0x0f01, 0xc9, CpuSSE3, NoSuf|ImmExt,  { 0, 0, 0} },
 /* mwait is very special. AX and CX are always 64bits with zero upper
    32bits in 64bit mode, and 32bits in 16bit and 32bit modes.  */
 /* Need to ensure only "mwait %eax,%ecx" is accepted.  */
-{"mwait",     2, 0x0f01, 0xc9, CpuPNI|CpuNo64, NoSuf|ImmExt,   { Reg32, Reg32, 0} },
+{"mwait",     2, 0x0f01, 0xc9, CpuSSE3|CpuNo64, NoSuf|ImmExt,  { Reg32, Reg32, 0} },
 /* Need to ensure only "mwait %rax,%rcx" is accepted.  */
-{"mwait",     2, 0x0f01, 0xc9, CpuPNI|Cpu64, NoSuf|ImmExt|NoRex64,     { Reg64, Reg64, 0} },
+{"mwait",     2, 0x0f01, 0xc9, CpuSSE3|Cpu64, NoSuf|ImmExt|NoRex64,    { Reg64, Reg64, 0} },
 
 /* VMX instructions.  */
 {"vmcall",    0, 0x0f01, 0xc1, CpuVMX, NoSuf|ImmExt,   { 0, 0, 0} },