boolean is_rv350 = r300->screen->caps.is_rv350;
boolean is_r500 = r300->screen->caps.is_r500;
boolean has_tcl = r300->screen->caps.has_tcl;
- boolean drm_2_6_0 = r300->screen->info.drm_minor >= 6;
/* Create the actual atom list.
*
R300_INIT_ATOM(gpu_flush, 9);
R300_INIT_ATOM(aa_state, 4);
R300_INIT_ATOM(fb_state, 0);
- R300_INIT_ATOM(hyperz_state, is_r500 || (is_rv350 && drm_2_6_0) ? 10 : 8);
+ R300_INIT_ATOM(hyperz_state, is_r500 || is_rv350 ? 10 : 8);
/* ZB (unpipelined), SC. */
R300_INIT_ATOM(ztop_state, 2);
/* ZB, FG. */
- R300_INIT_ATOM(dsa_state, is_r500 ? (drm_2_6_0 ? 10 : 8) : 6);
+ R300_INIT_ATOM(dsa_state, is_r500 ? 10 : 6);
/* RB3D. */
R300_INIT_ATOM(blend_state, 8);
R300_INIT_ATOM(blend_color_state, is_r500 ? 3 : 2);
OUT_CB_REG(R300_ZB_DEPTHCLEARVALUE, 0);
OUT_CB_REG(R300_SC_HYPERZ, R300_SC_HYPERZ_ADJ_2);
- if (r300->screen->caps.is_r500 ||
- (r300->screen->caps.is_rv350 &&
- r300->screen->info.drm_minor >= 6)) {
+ if (r300->screen->caps.is_r500 || r300->screen->caps.is_rv350) {
OUT_CB_REG(R300_GB_Z_PEQ_CONFIG, 0);
}
END_CB;
dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
if (r300->screen->caps.is_r500)
dwords += 2; /* emit_index_bias */
- if (r300->screen->info.drm_minor >= 6)
- dwords += 3; /* MSPOS */
+ dwords += 3; /* MSPOS */
return dwords;
}
r500_emit_index_bias(r300, 0);
/* The DDX doesn't set these regs. */
- if (r300->screen->info.drm_minor >= 6) {
+ {
CS_LOCALS(r300);
OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
OUT_CS(0x66666666);
{
struct r300_context *r300 = r300_context(pipe);
- if (r300->screen->info.drm_minor >= 12) {
- flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
- }
+ flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
if (r300->dirty_hw) {
r300_flush_and_cleanup(r300, flags, fence);
unsigned usage)
{
uint32_t retval = 0;
- boolean drm_2_8_0 = r300_screen(screen)->info.drm_minor >= 8;
boolean is_r500 = r300_screen(screen)->caps.is_r500;
boolean is_r400 = r300_screen(screen)->caps.is_r400;
boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
format == PIPE_FORMAT_RGTC2_SNORM ||
format == PIPE_FORMAT_LATC2_UNORM ||
format == PIPE_FORMAT_LATC2_SNORM;
- boolean is_x16f_xy16f = format == PIPE_FORMAT_R16_FLOAT ||
- format == PIPE_FORMAT_R16G16_FLOAT ||
- format == PIPE_FORMAT_A16_FLOAT ||
- format == PIPE_FORMAT_L16_FLOAT ||
- format == PIPE_FORMAT_L16A16_FLOAT ||
- format == PIPE_FORMAT_R16A16_FLOAT ||
- format == PIPE_FORMAT_I16_FLOAT;
boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
format == PIPE_FORMAT_R16G16_FLOAT ||
format == PIPE_FORMAT_R16G16B16_FLOAT ||
case 2:
case 4:
case 6:
- /* We need DRM 2.8.0. */
- if (!drm_2_8_0) {
- return FALSE;
- }
/* No texturing and scanout. */
if (usage & (PIPE_BIND_SAMPLER_VIEW |
PIPE_BIND_DISPLAY_TARGET |
(is_r500 || !is_ati1n) &&
/* ATI2N is supported on r4xx-r5xx. */
(is_r400 || is_r500 || !is_ati2n) &&
- /* R16F and RG16F texture support was added in as late as DRM 2.8.0 */
- (drm_2_8_0 || !is_x16f_xy16f) &&
r300_is_sampler_format_supported(format)) {
retval |= PIPE_BIND_SAMPLER_VIEW;
}
PIPE_BIND_SHARED |
PIPE_BIND_BLENDABLE)) &&
/* 2101010 cannot be rendered to on non-r5xx. */
- (!is_color2101010 || (is_r500 && drm_2_8_0)) &&
+ (!is_color2101010 || is_r500) &&
r300_is_colorbuffer_format_supported(format)) {
retval |= usage &
(PIPE_BIND_RENDER_TARGET |
if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
r300screen->caps.hiz_ram = 0;
- if (r300screen->info.drm_minor < 8)
- r300screen->caps.has_us_format = FALSE;
-
r300screen->rws = rws;
r300screen->screen.destroy = r300_destroy_screen;
r300screen->screen.get_name = r300_get_name;
r300_mark_atom_dirty(r300, &r300->dsa_state);
}
-static void r300_tex_set_tiling_flags(struct r300_context *r300,
- struct r300_resource *tex,
- unsigned level)
-{
- /* Check if the macrotile flag needs to be changed.
- * Skip changing the flags otherwise. */
- if (tex->tex.macrotile[tex->surface_level] !=
- tex->tex.macrotile[level]) {
- r300->rws->buffer_set_tiling(tex->buf, r300->cs,
- tex->tex.microtile, tex->tex.macrotile[level],
- 0, 0, 0, 0, 0, 0, 0,
- tex->tex.stride_in_bytes[0], false);
-
- tex->surface_level = level;
- }
-}
-
-/* This switcheroo is needed just because of goddamned MACRO_SWITCH. */
-static void r300_fb_set_tiling_flags(struct r300_context *r300,
- const struct pipe_framebuffer_state *state)
-{
- unsigned i;
-
- /* Set tiling flags for new surfaces. */
- for (i = 0; i < state->nr_cbufs; i++) {
- if (!state->cbufs[i])
- continue;
-
- r300_tex_set_tiling_flags(r300,
- r300_resource(state->cbufs[i]->texture),
- state->cbufs[i]->u.tex.level);
- }
- if (state->zsbuf) {
- r300_tex_set_tiling_flags(r300,
- r300_resource(state->zsbuf->texture),
- state->zsbuf->u.tex.level);
- }
-}
-
static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index,
const char *binding)
{
/* Re-swizzle the blend color. */
r300_set_blend_color(pipe, &((struct r300_blend_color_state*)r300->blend_color_state.state)->state);
- if (r300->screen->info.drm_minor < 12) {
- /* The tiling flags are dependent on the surface miplevel, unfortunately.
- * This workarounds a bad design decision in old kernels which were
- * rewriting tile fields in registers. */
- r300_fb_set_tiling_flags(r300, state);
- }
-
if (unlock_zbuffer) {
pipe_surface_reference(&r300->locked_zbuffer, NULL);
}