for _ in range(8):
yield
dut = AXILiteDUT()
- run_simulation(dut, generator(dut.dut), vcd_name='axi-write-read.vcd')
+ run_simulation(dut, generator(dut.dut))
def test_simultaneous(dut):
def generator(dut):
dut = AXILiteDUT()
- run_simulation(dut, generator(dut.dut), vcd_name='axi-simultaneous.vcd')
+ run_simulation(dut, generator(dut.dut))
data_generator(dut, dut.gearbox0, datas),
data_checker(dut, dut.gearbox1, datas)
]
- run_simulation(dut, generators, vcd_name="sim.vcd")
+ run_simulation(dut, generators)
self.assertEqual(dut.errors, 0)