build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to...

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
index 8b0986a57fd409eec261a85697c6278f66b0367d..9e90e3426258d35d4f03fef7559b866aecadbe55 100644 (file)
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@@ -134,7 +134,7 @@ xilinx_special_overrides = {
 class XilinxDDROutputImplS6(Module):
     def __init__(self, i1, i2, o, clk):
         self.specials += Instance("ODDR2",
-                p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="SYNC",
+                p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="ASYNC",
                 i_C0=clk, i_C1=~clk, i_CE=1, i_S=0, i_R=0,
                 i_D0=i1, i_D1=i2, o_Q=o,
         )