table corrections

diff --git a/simple_v_extension/sv_prefix_proposal.rst b/simple_v_extension/sv_prefix_proposal.rst
index 254a381cca888b646d8074fc9ddb32322075f9bb..fbbdf8fb5fc09149328dbd4a6736adf5c99e7cd7 100644 (file)
--- a/simple_v_extension/sv_prefix_proposal.rst
+++ b/simple_v_extension/sv_prefix_proposal.rst
@@ -55,7 +55,7 @@ First, bits 17:0:
 | Encoding      | 17     | 16         | 15         | 14  | 13         | 12          | 11:7 | 6          | 5:0    |
 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
 | P48-LD-type   | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
-+---------------+--------+------------+------------+--------------------------------+------+------------+--------+
++---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
 | P48-ST-type   |vitp7[6]| rs1[5]     | rs2[5]     | vs2 | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
 | P48-R-type    | rd[5]  | rs1[5]     | rs2[5]     | vs2 | vs1        | vitp6              | *Reserved* | 011111 |
@@ -102,7 +102,7 @@ bits 47:18 (RV32 shifted up by 16 bits):
 | P48-FR4-type  | RV32-FR-type  |
 +---------------+---------------+
 
-Separately, RV32 encodings:
+Table showing Standard RV32 encodings:
 
 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 | Encoding      | 31:27       | 26:25 | 24:20    | 19:15    | 14:12  | 11:7     | 6:2    | 1      | 0          |
@@ -123,7 +123,7 @@ Separately, RV32 encodings:
 64-bit Instruction Encodings
 ============================
 
-These extend the 48-bit encodings with the following additional bits:
+TODO (please disregard)
 
 +--------------+-------+-------+--------+--------+--------+----------+
 | Encoding     | 63:58 | 57    | 56     | 55     | 54     | 53:48    |
@@ -190,17 +190,17 @@ TODO: similar scheme for 64-bit encoding (incorporating extra bit rs#/rd[6] from
 Load/Store Kind (lsk) Field Encoding
 ====================================
 
-+------+----------+------------+-----------------------------------------------------------------+
-| vd/vs2 | vs1  | Meaning                                                         |
-+======+==========+============+=================================================================+
-| 0      | 0   | srcbase is scalar, LD/ST is pure scalar.                                                      |
-+------+----------+------------+-----------------------------------------------------------------+
-| 1     | 0   | srcbase is scalar, LD/ST is unit strided |
-+------+----------+------------+-----------------------------------------------------------------+
-| 0     | 1   | srcbase is a vector (gather/scatter aka array of srcbases). VSPLAT and VSELECT |
-+------+----------+------------+-----------------------------------------------------------------+
-| 1     | 1        | srcbase is a vector, LD/ST is a full vector LD/ST. |
-+------+----------+------------+-----------------------------------------------------------------+
++--------+-----+--------------------------------------------------------------------------------+
+| vd/vs2 | vs1 | Meaning                                                                        |
++========+=====+================================================================================+
+| 0      | 0   | srcbase is scalar, LD/ST is pure scalar.                                       |
++--------+-----+--------------------------------------------------------------------------------+
+| 1      | 0   | srcbase is scalar, LD/ST is unit strided                                       |
++--------+-----+--------------------------------------------------------------------------------+
+| 0      | 1   | srcbase is a vector (gather/scatter aka array of srcbases). VSPLAT and VSELECT |
++--------+-----+--------------------------------------------------------------------------------+
+| 1      | 1   | srcbase is a vector, LD/ST is a full vector LD/ST.                             |
++--------+-----+--------------------------------------------------------------------------------+
 
 Notes: