x86-64: also optimize ANDQ with immediate fitting in 7 bits

The same reasoning applies here as did/does for immediates fitting in
31 bits.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 41400b4629a70c0d22cc8b63b100a896735b13c6..416c2be4ecb34315e212f9fe77066bcb82f6566d 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2019-06-25  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (optimize_encoding): Also handle ANDQ with
+       immediatie fitting in 7 bits.
+       * testsuite/gas/i386/x86-64-optimize-1.s: Add ANDQ cases with
+       7- and 8-bit immediates.
+       * testsuite/gas/i386/x86-64-optimize-1.d: Adjust expectations.
+
 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 
        * testsuite/gas/i386/xmmword.s: Add cvtps2pi and cvttps2pi

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 050c87236a37c65174c7887bd007c1130a216a1a..39857561bdee412c57558a663626b6e5c767267d 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3948,7 +3948,10 @@ optimize_encoding (void)
                                && i.tm.extension_opcode == 0x4)
                            || ((i.tm.base_opcode == 0xf6
                                 || i.tm.base_opcode == 0xc6)
-                               && i.tm.extension_opcode == 0x0)))))
+                               && i.tm.extension_opcode == 0x0)))
+                   || (fits_in_imm7 (i.op[0].imms->X_add_number)
+                       && i.tm.base_opcode == 0x83
+                       && i.tm.extension_opcode == 0x4)))
               || (i.types[0].bitfield.qword
                   && ((i.reg_operands == 2
                        && i.op[0].regs == i.op[1].regs
@@ -3962,6 +3965,7 @@ optimize_encoding (void)
     {
       /* Optimize: -O:
           andq $imm31, %r64   -> andl $imm31, %r32
+          andq $imm7, %r64    -> andl $imm7, %r32
           testq $imm31, %r64  -> testl $imm31, %r32
           xorq %r64, %r64     -> xorl %r32, %r32
           subq %r64, %r64     -> subl %r32, %r32

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-1.d b/gas/testsuite/gas/i386/x86-64-optimize-1.d
index f7fd1beeeaa7f0cc811490e43e1bc6524e7fa488..aa612612fd386c667c140720a298aff178a7033f 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-1.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-1.d
@@ -15,6 +15,12 @@ Disassembly of section .text:
  +[a-f0-9]+:   48 25 00 00 00 80       and    \$0xffffffff80000000,%rax
  +[a-f0-9]+:   48 81 e3 00 00 00 80    and    \$0xffffffff80000000,%rbx
  +[a-f0-9]+:   49 81 e6 00 00 00 80    and    \$0xffffffff80000000,%r14
+ +[a-f0-9]+:   83 e0 7f                and    \$0x7f,%eax
+ +[a-f0-9]+:   83 e3 7f                and    \$0x7f,%ebx
+ +[a-f0-9]+:   41 83 e6 7f             and    \$0x7f,%r14d
+ +[a-f0-9]+:   48 83 e0 80             and    \$0xffffffffffffff80,%rax
+ +[a-f0-9]+:   48 83 e3 80             and    \$0xffffffffffffff80,%rbx
+ +[a-f0-9]+:   49 83 e6 80             and    \$0xffffffffffffff80,%r14
  +[a-f0-9]+:   a9 ff ff ff 7f          test   \$0x7fffffff,%eax
  +[a-f0-9]+:   f7 c3 ff ff ff 7f       test   \$0x7fffffff,%ebx
  +[a-f0-9]+:   41 f7 c6 ff ff ff 7f    test   \$0x7fffffff,%r14d

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-1.s b/gas/testsuite/gas/i386/x86-64-optimize-1.s
index 15d8cb05da81c12dad448c8e97b052da9321583a..b83ecb02da0aa3b867a06ceb8e6cb1ddb2f00775 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-1.s
+++ b/gas/testsuite/gas/i386/x86-64-optimize-1.s
@@ -10,6 +10,12 @@ _start:
        andq    $-((1<<31)), %rax
        andq    $-((1<<31)), %rbx
        andq    $-((1<<31)), %r14
+       andq    $((1<<7) - 1), %rax
+       andq    $((1<<7) - 1), %rbx
+       andq    $((1<<7) - 1), %r14
+       andq    $-((1<<7)), %rax
+       andq    $-((1<<7)), %rbx
+       andq    $-((1<<7)), %r14
        testq   $((1<<31) - 1), %rax
        testq   $((1<<31) - 1), %rbx
        testq   $((1<<31) - 1), %r14

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index da0d7abdb134fdb32ddde7079dc4a0fbf3495cb1..c4c3e9901d288c95847dbb14b28fea950170a811 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2019-06-25  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (and): Mark Imm8S form for optimization.
+       * i386-tbl.h: Re-generate.
+
 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-dis-evex.h: Break into ...

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index fc33555ae38ce56bd759c8997ff3d1c544124d0c..b40fa8ee7fc508a1599237a258c1ec3086f78751 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -209,7 +209,7 @@ test, 2, 0xa8, None, 1, 0, W|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32
 test, 2, 0xf6, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 
 and, 2, 0x20, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-and, 2, 0x83, 0x4, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+and, 2, 0x83, 0x4, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 and, 2, 0x24, None, 1, 0, W|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 and, 2, 0x80, 0x4, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 4244edec6d625f2a4c73d9ad54509ec2d0bd067f..e0bd4932550ba766702ecd6d13033fc159514696 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -1729,7 +1729,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
       1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0 } },