radeonsi,driconf: add clamp_div_by_zero option

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6259>

diff --git a/src/gallium/drivers/radeonsi/si_debug_options.h b/src/gallium/drivers/radeonsi/si_debug_options.h
index bf4329ad803540fcd9dccab57bfb7a7bd0f2e3a7..8df957f495fec5016a8dee192da6b71b094d4541 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_debug_options.h
+++ b/src/gallium/drivers/radeonsi/si_debug_options.h
@@ -8,5 +8,6 @@ OPT_BOOL(vs_fetch_always_opencode, false,
          "Always open code vertex fetches (less efficient, purely for testing)")
 OPT_BOOL(prim_restart_tri_strips_only, false, "Only enable primitive restart for triangle strips")
 OPT_BOOL(no_infinite_interp, false, "Kill PS with infinite interp coeff")
+OPT_BOOL(clamp_div_by_zero, false, "Clamp div by zero (x / 0 becomes FLT_MAX instead of NaN)")
 
 #undef OPT_BOOL

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index be73204f13224c8ff58f5446a4f8a41dab5ec7cb..68e6623608b61215ed1cfc478954c2331b12a344 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -907,7 +907,7 @@ static void si_disk_cache_create(struct si_screen *sscreen)
    disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
 
 /* These flags affect shader compilation. */
-#define ALL_FLAGS (DBG(GISEL) | DBG(KILL_PS_INF_INTERP))
+#define ALL_FLAGS (DBG(GISEL) | DBG(KILL_PS_INF_INTERP) | DBG(CLAMP_DIV_BY_ZERO))
    uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
 
    /* Add the high bits of 32-bit addresses, which affects
@@ -1030,9 +1030,10 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
 #include "si_debug_options.h"
    }
 
-   if (sscreen->options.no_infinite_interp) {
+   if (sscreen->options.no_infinite_interp)
       sscreen->debug_flags |= DBG(KILL_PS_INF_INTERP);
-   }
+   if (sscreen->options.clamp_div_by_zero)
+      sscreen->debug_flags |= DBG(CLAMP_DIV_BY_ZERO);
 
    si_disk_cache_create(sscreen);
 

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 490dc13d30fd7eac5de20f28454b465166ccc029..88a77542f1a51ed3b68f4f34d66f6b159fe77b8a 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -162,6 +162,7 @@ enum
    DBG_W64_PS,
    DBG_W64_CS,
    DBG_KILL_PS_INF_INTERP,
+   DBG_CLAMP_DIV_BY_ZERO,
 
    /* Shader compiler options (with no effect on the shader cache): */
    DBG_CHECK_IR,

diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c
index 18ce02e151caec772a95dbf368c9c02332473430..b4f62735b9467d7e8af4c68074e16c0ce6db512d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_llvm.c
+++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c
@@ -460,6 +460,7 @@ bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
    ctx->abi.clamp_shadow_reference = true;
    ctx->abi.robust_buffer_access = true;
    ctx->abi.convert_undef_to_zero = true;
+   ctx->abi.clamp_div_by_zero = ctx->screen->options.clamp_div_by_zero;
 
    if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
       assert(gl_shader_stage_is_compute(nir->info.stage));