---------- Begin Simulation Statistics ----------
-host_inst_rate 1892986 # Simulator instruction rate (inst/s)
-host_mem_usage 370804 # Number of bytes of host memory used
-host_seconds 214.81 # Real time elapsed on the host
-host_tick_rate 23798444654 # Simulator tick rate (ticks/s)
+host_inst_rate 2446370 # Simulator instruction rate (inst/s)
+host_mem_usage 368136 # Number of bytes of host memory used
+host_seconds 166.22 # Real time elapsed on the host
+host_tick_rate 30755543746 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 406624453 # Number of instructions simulated
+sim_insts 406624458 # Number of instructions simulated
sim_seconds 5.112051 # Number of seconds simulated
-sim_ticks 5112051463500 # Number of ticks simulated
+sim_ticks 5112051446000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses::0 13367989 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13367989 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::0 12053700 # number of ReadReq hits
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-system.cpu.dcache.ReadReq_miss_rate::0 0.098316 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 1314289 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1314289 # number of ReadReq misses
+system.cpu.dcache.ReadReq_hits::0 12059464 # number of ReadReq hits
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+system.cpu.dcache.ReadReq_miss_rate::0 0.097885 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_accesses::0 8403116 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8403116 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0 8087096 # number of WriteReq hits
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-system.cpu.dcache.WriteReq_miss_rate::0 0.037607 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 316020 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 316020 # number of WriteReq misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
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system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 20140796 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses::0 21771105 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21771105 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits::1 0 # number of overall hits
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system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
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system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 1620657 # number of replacements
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.980804 # Cycle average of tags in use
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system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 1525412 # number of writebacks
-system.cpu.dtb_walker_cache.ReadExReq_accesses::1 21821 # number of ReadExReq accesses(hits+misses)
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-system.cpu.dtb_walker_cache.ReadExReq_miss_rate::1 0.627927 # miss rate for ReadExReq accesses
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system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dtb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::1 21821 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 21821 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits
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system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dtb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.replacements 7920 # number of replacements
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system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dtb_walker_cache.tagsinuse 5.005513 # Cycle average of tags in use
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-system.cpu.dtb_walker_cache.warmup_cycle 5101233174000 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.writebacks 7801 # number of writebacks
-system.cpu.icache.ReadReq_accesses::0 254189384 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_misses::total 792421 # number of ReadReq misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
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system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
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system.cpu.icache.sampled_refs 792414 # Sample count of references to valid blocks.
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system.cpu.icache.warmup_cycle 148756026000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 809 # number of writebacks
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system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::1 3755 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total 3755 # number of demand (read+write) hits
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system.cpu.itb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::1 0.692692 # miss rate for demand accesses
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system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::1 8464 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total 8464 # number of demand (read+write) misses
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system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.itb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.occ_%::1 0.063695 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_blocks::1 1.019121 # Average occupied blocks per context
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system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::1 12219 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 12219 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits
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system.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
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system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses
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-system.cpu.itb_walker_cache.overall_misses::total 8464 # number of overall misses
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system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.itb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.itb_walker_cache.replacements 3371 # number of replacements
-system.cpu.itb_walker_cache.sampled_refs 3379 # Sample count of references to valid blocks.
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system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.itb_walker_cache.tagsinuse 1.019121 # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs 5341 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5105336019500 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.writebacks 3369 # number of writebacks
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+system.cpu.itb_walker_cache.warmup_cycle 5105305893500 # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.writebacks 603 # number of writebacks
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
-system.cpu.numCycles 10224102950 # number of cpu cycles simulated
+system.cpu.numCycles 10224102915 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 453482138.002058 # Number of busy cycles
-system.cpu.num_conditional_control_insts 42460206 # number of instructions that are conditional controls
+system.cpu.num_busy_cycles 453482144.002058 # Number of busy cycles
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 9770620811.997942 # Number of idle cycles
-system.cpu.num_insts 406624453 # Number of instructions executed
-system.cpu.num_int_alu_accesses 391833833 # Number of integer alu accesses
-system.cpu.num_int_insts 391833833 # number of integer instructions
-system.cpu.num_int_register_reads 836347867 # number of times the integer registers were read
-system.cpu.num_int_register_writes 419160860 # number of times the integer registers were written
+system.cpu.num_idle_cycles 9770620770.997942 # Number of idle cycles
+system.cpu.num_insts 406624458 # Number of instructions executed
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+system.cpu.num_int_insts 391833838 # number of integer instructions
+system.cpu.num_int_register_reads 836347889 # number of times the integer registers were read
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system.cpu.num_load_insts 29720540 # Number of load instructions
system.cpu.num_mem_refs 38133606 # number of memory refs
system.cpu.num_store_insts 8413066 # Number of store instructions
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 4994772176509 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 46667 # number of writebacks
-system.l2c.ReadExReq_accesses::0 314094 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1 10676 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 324770 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits::0 169175 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1 9794 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 178969 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate::0 0.461387 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1 0.082615 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.544003 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 144919 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1 882 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 145801 # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0 2100004 # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_hits::0 2043710 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2043710 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0 0.026807 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 56294 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 56294 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses::0 33 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 3893 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 3926 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_hits::0 2 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1 1 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_rate::0 0.939394 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 0.999743 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 1.939137 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 31 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1 3892 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3923 # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0 1537391 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1537391 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 1537391 # number of Writeback hits
-system.l2c.Writeback_hits::total 1537391 # number of Writeback hits
+system.l2c.ReadExReq_accesses::0 314040 # number of ReadExReq accesses(hits+misses)
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+system.l2c.UpgradeReq_misses::total 1797 # number of UpgradeReq misses
+system.l2c.Writeback_accesses::0 1530354 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 1530354 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 1530354 # number of Writeback hits
+system.l2c.Writeback_hits::total 1530354 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 16.898474 # Average number of references to valid blocks.
+system.l2c.avg_refs 16.953097 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 2414098 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 10676 # number of demand (read+write) accesses
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system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits::0 2212885 # number of demand (read+write) hits
-system.l2c.demand_hits::1 9794 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2222679 # number of demand (read+write) hits
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system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.083349 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.082615 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.165964 # miss rate for demand accesses
-system.l2c.demand_misses::0 201213 # number of demand (read+write) misses
-system.l2c.demand_misses::1 882 # number of demand (read+write) misses
-system.l2c.demand_misses::total 202095 # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0 0.083196 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.002631 # miss rate for demand accesses
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+system.l2c.demand_misses::total 200887 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.147969 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.414145 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 9697.290249 # Average occupied blocks per context
-system.l2c.occ_blocks::1 27141.433510 # Average occupied blocks per context
-system.l2c.overall_accesses::0 2414098 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 10676 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2424774 # number of overall (read+write) accesses
+system.l2c.occ_%::0 0.147971 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.414180 # Average percentage of cache occupancy
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system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 2212885 # number of overall hits
-system.l2c.overall_hits::1 9794 # number of overall hits
-system.l2c.overall_hits::total 2222679 # number of overall hits
+system.l2c.overall_hits::0 2213441 # number of overall hits
+system.l2c.overall_hits::1 10235 # number of overall hits
+system.l2c.overall_hits::total 2223676 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.083349 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.082615 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.165964 # miss rate for overall accesses
-system.l2c.overall_misses::0 201213 # number of overall misses
-system.l2c.overall_misses::1 882 # number of overall misses
-system.l2c.overall_misses::total 202095 # number of overall misses
+system.l2c.overall_miss_rate::0 0.083196 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.002631 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.085827 # miss rate for overall accesses
+system.l2c.overall_misses::0 200860 # number of overall misses
+system.l2c.overall_misses::1 27 # number of overall misses
+system.l2c.overall_misses::total 200887 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 164866 # number of replacements
-system.l2c.sampled_refs 196728 # Sample count of references to valid blocks.
+system.l2c.replacements 164351 # number of replacements
+system.l2c.sampled_refs 196384 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 36838.723760 # Cycle average of tags in use
-system.l2c.total_refs 3324403 # Total number of references to valid blocks.
+system.l2c.tagsinuse 36841.181126 # Cycle average of tags in use
+system.l2c.total_refs 3329317 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 144396 # number of writebacks
+system.l2c.writebacks 144194 # number of writebacks
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
---------- Begin Simulation Statistics ----------
-host_inst_rate 1227876 # Simulator instruction rate (inst/s)
-host_mem_usage 367348 # Number of bytes of host memory used
-host_seconds 215.31 # Real time elapsed on the host
-host_tick_rate 24093749418 # Simulator tick rate (ticks/s)
+host_inst_rate 1546136 # Simulator instruction rate (inst/s)
+host_mem_usage 364716 # Number of bytes of host memory used
+host_seconds 170.97 # Real time elapsed on the host
+host_tick_rate 30388572127 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 264367743 # Number of instructions simulated
-sim_seconds 5.187507 # Number of seconds simulated
-sim_ticks 5187506658000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses::0 13293064 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13293064 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15104.781562 # average ReadReq miss latency
+sim_insts 264339287 # Number of instructions simulated
+sim_seconds 5.195470 # Number of seconds simulated
+sim_ticks 5195470393000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses::0 13288006 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 15144.526649 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12104.746605 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12144.494227 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0 11977155 # number of ReadReq hits
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
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system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency
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system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency
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system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits
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system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::1 19730.086428 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::1 11042.372881 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 16730.086428 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::1 3771 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total 3771 # number of overall hits
-system.cpu.itb_walker_cache.overall_miss_latency 168929000 # number of overall miss cycles
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system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::1 0.694235 # miss rate for overall accesses
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system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::1 8562 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total 8562 # number of overall misses
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system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.itb_walker_cache.overall_mshr_miss_latency 143243000 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency 37011000 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.694235 # mshr miss rate for overall accesses
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system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_misses 8562 # number of overall MSHR misses
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system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.itb_walker_cache.replacements 3493 # number of replacements
-system.cpu.itb_walker_cache.sampled_refs 3500 # Sample count of references to valid blocks.
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+system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.itb_walker_cache.tagsinuse 1.043665 # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs 5305 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5175757784000 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.writebacks 3491 # number of writebacks
+system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use
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+system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.writebacks 826 # number of writebacks
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.not_idle_fraction 0.058188 # Percentage of non-idle cycles
-system.cpu.numCycles 10375013316 # number of cpu cycles simulated
+system.cpu.not_idle_fraction 0.058047 # Percentage of non-idle cycles
+system.cpu.numCycles 10390940786 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 603697441.873884 # Number of busy cycles
-system.cpu.num_conditional_control_insts 24882902 # number of instructions that are conditional controls
+system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles
+system.cpu.num_conditional_control_insts 24882695 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 9771315874.126116 # Number of idle cycles
-system.cpu.num_insts 264367743 # Number of instructions executed
-system.cpu.num_int_alu_accesses 249584659 # Number of integer alu accesses
-system.cpu.num_int_insts 249584659 # number of integer instructions
-system.cpu.num_int_register_reads 543556622 # number of times the integer registers were read
-system.cpu.num_int_register_writes 266062505 # number of times the integer registers were written
-system.cpu.num_load_insts 14817593 # Number of load instructions
-system.cpu.num_mem_refs 23178416 # number of memory refs
-system.cpu.num_store_insts 8360823 # Number of store instructions
-system.iocache.ReadReq_accesses::1 838 # number of ReadReq accesses(hits+misses)
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+system.cpu.num_int_register_writes 266037487 # number of times the integer registers were written
+system.cpu.num_load_insts 14812525 # Number of load instructions
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system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 126350.754177 # average ReadReq miss latency
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system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 74325.749403 # average ReadReq mshr miss latency
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system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
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system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_misses 838 # number of ReadReq MSHR misses
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system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 136919.759418 # average WriteReq miss latency
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system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 84914.276498 # average WriteReq mshr miss latency
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system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
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system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses
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system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs 11300 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
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system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
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system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 84727.700408 # average overall mshr miss latency
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system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 6502773092 # number of demand (read+write) miss cycles
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system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
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system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.occ_%::1 0.006011 # Average percentage of cache occupancy
-system.iocache.occ_blocks::1 0.096172 # Average occupied blocks per context
+system.iocache.occ_%::1 0.007537 # Average percentage of cache occupancy
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system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
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system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
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system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
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system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.iocache.overall_hits::0 0 # number of overall hits
system.iocache.overall_hits::1 0 # number of overall hits
system.iocache.overall_hits::total 0 # number of overall hits
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system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
system.iocache.overall_misses::0 0 # number of overall misses
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system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
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system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
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system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.replacements 47503 # number of replacements
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+system.iocache.replacements 47510 # number of replacements
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system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0.096172 # Cycle average of tags in use
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system.iocache.total_refs 0 # Total number of references to valid blocks.
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-system.iocache.writebacks 46667 # number of writebacks
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-system.l2c.ReadExReq_avg_miss_latency::0 52450.939745 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 6116197.957198 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 6168648.896943 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40004.929653 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0 193117 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1 9319 # number of ReadExReq hits
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-system.l2c.ReadExReq_miss_latency 6287451500 # number of ReadExReq miss cycles
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-system.l2c.ReadExReq_misses::1 1028 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 120901 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 4836636000 # number of ReadExReq MSHR miss cycles
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-system.l2c.ReadExReq_mshr_miss_rate::1 11.684643 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 12.070920 # mshr miss rate for ReadExReq accesses
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-system.l2c.ReadReq_avg_miss_latency::0 52255.661117 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40255.279138 # average ReadReq mshr miss latency
+system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit.
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+system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
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+system.l2c.ReadReq_avg_miss_latency::1 115483586.956522 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 115535865.628752 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40254.652764 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0 2048617 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2048617 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 2667651500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.024313 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 51050 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 51050 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 2055032000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.024313 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 51050 # number of ReadReq MSHR misses
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+system.l2c.ReadReq_hits::1 9561 # number of ReadReq hits
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+system.l2c.ReadReq_miss_latency 2656122500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0 0.024209 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.002400 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.026609 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 50807 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 23 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses
+system.l2c.ReadReq_mshr_miss_latency 2046144000 # number of ReadReq MSHR miss cycles
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+system.l2c.ReadReq_mshr_miss_rate::1 5.303631 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 5.327851 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 50830 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 56051785000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses::0 69 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 3915 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 3984 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 29000 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 507.071227 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 29507.071227 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40103.613849 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0 1 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1 26 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 27 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency 1972000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 0.985507 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 0.993359 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 1.978866 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 68 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1 3889 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3957 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 158690000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0 57.347826 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 1.010728 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 58.358554 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 3957 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_accesses::0 1689 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 24673.484295 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40254.930606 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0 320 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_latency 33778000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate::0 0.810539 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 1369 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 55109000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0 0.810539 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 1369 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1218002000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 1539352 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1539352 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 1539352 # number of Writeback hits
-system.l2c.Writeback_hits::total 1539352 # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency 1218050000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0 1534567 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 1534567 # number of Writeback hits
+system.l2c.Writeback_hits::total 1534567 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 19.863119 # Average number of references to valid blocks.
+system.l2c.avg_refs 19.991025 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 2412657 # number of demand (read+write) accesses
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-system.l2c.demand_accesses::total 2423004 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 52392.615388 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 8711189.688716 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 8763582.304104 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40079.255137 # average overall mshr miss latency
-system.l2c.demand_hits::0 2241734 # number of demand (read+write) hits
-system.l2c.demand_hits::1 9319 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2251053 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 8955103000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.070844 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.099352 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.170197 # miss rate for demand accesses
-system.l2c.demand_misses::0 170923 # number of demand (read+write) misses
-system.l2c.demand_misses::1 1028 # number of demand (read+write) misses
-system.l2c.demand_misses::total 171951 # number of demand (read+write) misses
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+system.l2c.demand_avg_miss_latency::0 52086.252376 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 387193347.826087 # average overall miss latency
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+system.l2c.demand_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency
+system.l2c.demand_hits::0 2240840 # number of demand (read+write) hits
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+system.l2c.demand_miss_latency 8905447000 # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_rate::1 0.002400 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.073290 # miss rate for demand accesses
+system.l2c.demand_misses::0 170975 # number of demand (read+write) misses
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+system.l2c.demand_misses::total 170998 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 6891668000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.071270 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 16.618440 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 16.689711 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 171951 # number of demand (read+write) MSHR misses
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+system.l2c.demand_mshr_miss_rate::0 0.070900 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 17.842028 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 17.912929 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 170998 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.120535 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.358282 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 7899.412034 # Average occupied blocks per context
-system.l2c.occ_blocks::1 23480.375714 # Average occupied blocks per context
-system.l2c.overall_accesses::0 2412657 # number of overall (read+write) accesses
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-system.l2c.overall_avg_miss_latency::0 52392.615388 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 8711189.688716 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 8763582.304104 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40079.255137 # average overall mshr miss latency
+system.l2c.occ_%::0 0.120711 # Average percentage of cache occupancy
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+system.l2c.occ_blocks::0 7910.895776 # Average occupied blocks per context
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system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 2241734 # number of overall hits
-system.l2c.overall_hits::1 9319 # number of overall hits
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+system.l2c.overall_miss_rate::1 0.002400 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.073290 # miss rate for overall accesses
+system.l2c.overall_misses::0 170975 # number of overall misses
+system.l2c.overall_misses::1 23 # number of overall misses
+system.l2c.overall_misses::total 170998 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 6891668000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.071270 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 16.618440 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 16.689711 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 171951 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 57269787000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency 6853449000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0 0.070900 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 17.842028 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 17.912929 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 170998 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 57269835000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 135636 # number of replacements
-system.l2c.sampled_refs 168555 # Sample count of references to valid blocks.
+system.l2c.replacements 136133 # number of replacements
+system.l2c.sampled_refs 168244 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 31379.787748 # Cycle average of tags in use
-system.l2c.total_refs 3348028 # Total number of references to valid blocks.
+system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use
+system.l2c.total_refs 3363370 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 115407 # number of writebacks
+system.l2c.writebacks 116255 # number of writebacks
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
projects / gem5.git / commitdiff