r600g: move initialization of use_surface flag into screen_create

Also change the type to bool and give it a less ambiguous name.

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 7cf6038bf587036896692433370ce99b76ebdae4..81366e56dacf46e707d78bd84a86cc4b1b49cd00 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -955,7 +955,7 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 
        endian = r600_colorformat_endian_swap(format);
 
-       if (!rscreen->use_surface) {
+       if (!rscreen->use_surface_alloc) {
                height = texture->height0;
                depth = texture->depth0;
                width = texture->width0;
@@ -1278,7 +1278,7 @@ static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rsta
        }
 
        /* XXX quite sure for dx10+ hw don't need any offset hacks */
-       if (!rscreen->use_surface) {
+       if (!rscreen->use_surface_alloc) {
                offset = r600_texture_get_offset(rtex,
                                level, state->cbufs[cb]->u.tex.first_layer);
                pitch = rtex->pitch_in_blocks[level] / 8 - 1;
@@ -1444,7 +1444,7 @@ static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rsta
                                R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
                                S_028C68_SLICE_TILE_MAX(slice),
                                NULL, 0);
-       if (!rscreen->use_surface) {
+       if (!rscreen->use_surface_alloc) {
                r600_pipe_state_add_reg(rstate,
                                        R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
                                        0x00000000, NULL, 0);
@@ -1488,7 +1488,7 @@ static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rsta
 
        offset = r600_resource_va(rctx->context.screen, surf->base.texture);
        /* XXX remove this once tiling is properly supported */
-       if (!rscreen->use_surface) {
+       if (!rscreen->use_surface_alloc) {
                /* XXX remove this once tiling is properly supported */
                array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
                                V_028C70_ARRAY_1D_TILED_THIN1;
@@ -1545,7 +1545,7 @@ static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rsta
                                offset, &rtex->resource, RADEON_USAGE_READWRITE);
        r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
                                offset, &rtex->resource, RADEON_USAGE_READWRITE);
-       if (!rscreen->use_surface) {
+       if (!rscreen->use_surface_alloc) {
                r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
                                        0x00000000, NULL, 0);
        } else {
@@ -1572,7 +1572,7 @@ static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rsta
                                        1 | S_028044_TILE_SPLIT(stile_split),
                                        &rtex->stencil->resource, RADEON_USAGE_READWRITE);
        } else {
-               if (rscreen->use_surface && rtex->surface.flags & RADEON_SURF_SBUFFER) {
+               if (rscreen->use_surface_alloc && rtex->surface.flags & RADEON_SURF_SBUFFER) {
                        uint64_t stencil_offset = rtex->surface.stencil_offset;
                        unsigned stile_split = rtex->surface.stencil_tile_split;
 

diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 7c828041f83437151919a5823eb616cf27cf3f06..3a68d479cf01e11f300d85b4ddd083dc3390bf74 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -856,5 +856,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
        LIST_INITHEAD(&rscreen->fences.blocks);
        pipe_mutex_init(rscreen->fences.mutex);
 
+       rscreen->use_surface_alloc = debug_get_bool_option("R600_SURF", TRUE);
+
        return &rscreen->screen;
 }

diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 8a4731d7e1f8f34988aa098b0e78cde9a2ddbe76..bb6f2416aa10b0f5d96d575867e73d81bfe817b6 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -131,7 +131,7 @@ struct r600_screen {
        struct r600_pipe_fences         fences;
 
        unsigned                        num_contexts;
-       unsigned                        use_surface;
+       bool                            use_surface_alloc;
 
        /* for thread-safe write accessing to num_contexts */
        pipe_mutex                      mutex_num_contexts;

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index dee6dc19d688651892e0319592e3b6de88a0feed..170d46127047274fbedb66ca707c243b094b0d3c 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -959,7 +959,7 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 
        offset_level = state->u.tex.first_level;
        last_level = state->u.tex.last_level - offset_level;
-       if (!rscreen->use_surface) {
+       if (!rscreen->use_surface_alloc) {
                width = u_minify(texture->width0, offset_level);
                height = u_minify(texture->height0, offset_level);
                depth = u_minify(texture->depth0, offset_level);
@@ -1349,7 +1349,7 @@ static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
        }
 
        /* XXX quite sure for dx10+ hw don't need any offset hacks */
-       if (!rscreen->use_surface) {
+       if (!rscreen->use_surface_alloc) {
                offset = r600_texture_get_offset(rtex,
                                                 level, state->cbufs[cb]->u.tex.first_layer);
                pitch = rtex->pitch_in_blocks[level] / 8 - 1;
@@ -1475,7 +1475,7 @@ static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
                                S_028060_PITCH_TILE_MAX(pitch) |
                                S_028060_SLICE_TILE_MAX(slice),
                                NULL, 0);
-       if (!rscreen->use_surface) {
+       if (!rscreen->use_surface_alloc) {
                r600_pipe_state_add_reg(rstate,
                                        R_028080_CB_COLOR0_VIEW + cb * 4,
                                        0x00000000, NULL, 0);
@@ -1516,7 +1516,7 @@ static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
        surf = (struct r600_surface *)state->zsbuf;
        rtex = (struct r600_resource_texture*)state->zsbuf->texture;
 
-       if (!rscreen->use_surface) {
+       if (!rscreen->use_surface_alloc) {
                /* XXX remove this once tiling is properly supported */
                array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
                        V_0280A0_ARRAY_1D_TILED_THIN1;
@@ -1556,7 +1556,7 @@ static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
        r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
                                S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
                                NULL, 0);
-       if (!rscreen->use_surface) {
+       if (!rscreen->use_surface_alloc) {
                r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, NULL, 0);
        } else {
                r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW,

diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 90edabb719085458afe193e4d8400ba0babeaddf..54d7c91b5c91c2eb95a17ee08f454f49da5cd55f 100644 (file)
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -494,8 +494,6 @@ static const struct u_resource_vtbl r600_texture_vtbl =
        u_default_transfer_inline_write /* transfer_inline_write */
 };
 
-DEBUG_GET_ONCE_BOOL_OPTION(use_surface, "R600_SURF", TRUE);
-
 static struct r600_resource_texture *
 r600_texture_create_object(struct pipe_screen *screen,
                           const struct pipe_resource *base,
@@ -511,13 +509,6 @@ r600_texture_create_object(struct pipe_screen *screen,
        struct r600_screen *rscreen = (struct r600_screen*)screen;
        int r;
 
-       /* FIXME ugly temporary hack to allow to switch btw current code
-        * and common surface allocator code
-        */
-       if (debug_get_option_use_surface()) {
-               rscreen->use_surface = 1;
-       }
-
        rtex = CALLOC_STRUCT(r600_resource_texture);
        if (rtex == NULL)
                return NULL;
@@ -534,7 +525,7 @@ r600_texture_create_object(struct pipe_screen *screen,
        if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) &&
            ((struct r600_screen*)screen)->chip_class >= EVERGREEN &&
            util_format_is_depth_and_stencil(base->format) &&
-           !rscreen->use_surface) {
+           !rscreen->use_surface_alloc) {
                struct pipe_resource stencil;
                unsigned stencil_pitch_override = 0;
 
@@ -579,7 +570,7 @@ r600_texture_create_object(struct pipe_screen *screen,
                rtex->is_depth = true;
 
        r600_setup_miptree(screen, rtex, array_mode);
-       if (rscreen->use_surface) {
+       if (rscreen->use_surface_alloc) {
                rtex->surface = *surface;
                r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
                if (r) {
@@ -606,7 +597,7 @@ r600_texture_create_object(struct pipe_screen *screen,
                struct pipe_resource *ptex = &rtex->resource.b.b.b;
                unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 
-               if (rscreen->use_surface) {
+               if (rscreen->use_surface_alloc) {
                        base_align = rtex->surface.bo_alignment;
                } else if (util_format_is_depth_or_stencil(rtex->real_format)) {
                        /* ugly work around depth buffer need stencil room at end of bo */
@@ -641,7 +632,7 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 
        if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
            !(templ->bind & PIPE_BIND_SCANOUT)) {
-               if (rscreen->use_surface) {
+               if (rscreen->use_surface_alloc) {
                        if (permit_hardware_blit(screen, templ)) {
                                array_mode = V_038000_ARRAY_2D_TILED_THIN1;
                        }