doc: minor edits

diff --git a/doc/introduction.rst b/doc/introduction.rst
index abc68ee01a2ee5a64e66af1043fda36bf3f60f58..bc24e336d63a9d0bb93e5e2782fab35f9ac39c79 100644 (file)
--- a/doc/introduction.rst
+++ b/doc/introduction.rst
@@ -38,17 +38,23 @@ Even though the Milkymist system-on-chip [mm]_ had many successes, it suffers fr
    #. Building a memory infrastructure (including bus interconnect, bridges and caches) that can automatically adapt itself at compile-time to any word size of the SDRAM is clumsy and tedious.
    #. Building register banks for control, status and interrupt management of cores can also largely benefit from automation.
    #. Many hardware acceleration problems can fit into the dataflow programming model. Manual dataflow implementation in V*HDL has, again, a lot of redundancy and potential for human errors. See the Milkymist texture mapping unit [mthesis]_ [mxcell]_ for an example of this. The amount of detail to deal with manually also makes the design space exploration difficult, and therefore hinders the design of efficient architectures.
-   #. Pre-computation of values, such as filter coefficients for DSP or even simply trigonometric tables, must often be done using external tools whose results are copy-and-pasted (in the best cases, automatically) into the V*HDL source.
+   #. Pre-computation of values, such as filter coefficients for DSP or even simply trigonometric tables, must often be done using external tools whose results are copy-and-pasted (in the best case, automatically) into the V*HDL source.
 
 .. [mthesis] http://m-labs.hk/thesis/thesis.pdf
 .. [mxcell] http://www.xilinx.com/publications/archives/xcell/Xcell77.pdf p30-35
    
 Enter Migen, a Python toolbox for building complex digital hardware. We could have designed a brand new programming language, but that would have been reinventing the wheel instead of being able to benefit from Python's rich features and immense library. The price to pay is a slightly cluttered syntax at times when writing descriptions in FHDL, but we believe this is totally acceptable, particularly when compared to VHDL ;-)
 
-Migen is made up of several related components, which are described in this manual.
+Migen is made up of several related components:
+
+#. the base language, FHDL
+#. a library of small generic cores
+#. a simulator
+#. a build system
 
 Installing Migen
 ****************
+
 Either run the ``setup.py`` installation script or simply set ``PYTHONPATH`` to the root of the source directory.
 
 If you wish to contribute patches, the suggest way to install is;

diff --git a/doc/simulation.rst b/doc/simulation.rst
index 8f392d9c7b2bd35bb94904e400a214f9db7498db..eff0ba5f7a3de758ed4ee4f6ee23654c6301b577 100644 (file)
--- a/doc/simulation.rst
+++ b/doc/simulation.rst
@@ -1,6 +1,6 @@
 Simulating a Migen design
 #########################
 
-Migen allows you to easily simulate your FHDL design and interface it with arbitrary Python code.
+Migen allows you to easily simulate your FHDL design and interface it with arbitrary Python code. The simulator is written in pure Python and interprets the FHDL structure directly without using an external Verilog simulator.
 
 [To be rewritten]