radv: allow clear merging for depth/stencil with no care stencil

Some of the Sascha Willems demos pick a D32/S8 format for the depth
buffer, then do a LOAD_OP_CLEAR/LOAD_OP_DONT_CARE on it, which means
we don't get to merge the undefined->depth and clear htile transitions.

This add the stencil aspect to the pending clears if there is a depth
clear pending and the stencil aspect is don't care.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index a2578126c5259db853cfc20798308b651386a800..9c20bb003c4befa6a90331d36267c9a60201c3c5 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1824,6 +1824,9 @@ radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
                        if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
                            att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
                                clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
+                               if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
+                                   att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
+                                       clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
                        }
                        if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
                            att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {