back.rtlil: it is not necessary to match binop operand width.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index e7ec34c44c135f635baa0d6c339b30fbfb2e0421..298d2f9fc5eb17d1c9c569843e3bb7adc70281e8 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -490,7 +490,6 @@ class _RHSValueCompiler(_ValueCompiler):
             rhs_wire = self(rhs)
         else:
             lhs_sign = rhs_sign = True
-            lhs_bits = rhs_bits = max(lhs_bits, rhs_bits)
             lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
             rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
         res_bits, res_sign = value.shape()